公开(公告)号：JP2002141948A

公开(公告)日：2002-05-17

申请号：JP2001281049

申请日：2001-09-17

Applicant: IBM

Inventor： LUIJTEN RONALD P ,  MINKENBERG CYRIEL ,  SCHUMACHER NORBERT ,  JUERGEN KEHR ,  LEPPLA BERND

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To provide a switching configuration to transport a data packet including data packet destination information and a payload to one output port or more. SOLUTION: Each input port 20 of a switching device 10 has an output buffer 35 that stores a payload of each data packet arrived in each input port 20 to its address. Furthermore, each input port 20 is provided with output queues whose number is the same as that of output ports 30. Each output queue stores addresses of each payload stored in the output buffer 35 and they are classified depending on data packet destination information. The stored payload can be sent to at least one of the output ports 30 under the use of the stored addresses at the point of time and pointed out by the addresses.

公开(公告)号：DE4342521C1

公开(公告)日：1995-07-13

申请号：DE4342521

申请日：1993-12-14

Applicant: IBM

Inventor： KOEHLER THOMAS ,  GETZLAFF KLAUS JOERG ,  KOESTER RALPH ,  STOEHR TILMANN ,  KOHLER HELMUT ,  SCHUMACHER NORBERT

IPC: H03M7/30 ,  G06F17/00

Abstract: The method uses source and target registers (15,16,26 to 29) to alternately receive and take out data blocks of predefined lengths. Index symbols are selected from the contacts of the source register and used as addresses of dictionary memory (14) whose entries contain expanded data in the form of variable length character symbols. Data blocks of predefined lengths are formed from the character symbols and stored in target registers. A divider (22), a multiplexer circuit and control circuit dynamically select the target register to alternately load the target register and transmit complete data blocks to memory.

公开(公告)号：DE60119866T2

公开(公告)日：2007-05-10

申请号：DE60119866

申请日：2001-09-08

Applicant: IBM

Inventor： MINKENBERG CYRIEL ,  LUIJTEN RONALD P ,  KOEHL JUERGEN ,  LEPPLA BERND ,  SCHUMACHER NORBERT

IPC: H04L49/111 ,  H04Q11/04

Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.

公开(公告)号：DE60317890T2

公开(公告)日：2008-11-27

申请号：DE60317890

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：DE60317890D1

公开(公告)日：2008-01-17

申请号：DE60317890

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：AU2003215841A1

公开(公告)日：2003-11-17

申请号：AU2003215841

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：DE60119866D1

公开(公告)日：2006-06-29

申请号：DE60119866

申请日：2001-09-08

Applicant: IBM

Inventor： MINKENBERG CYRIEL ,  LUIJTEN RONALD P ,  KOEHL JUERGEN ,  LEPPLA BERND ,  SCHUMACHER NORBERT

IPC: H04L49/111 ,  H04Q11/04

Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.