METHOD AND SYSTEM FOR ISSUING INSTRUCTION

    公开(公告)号:JPH10283178A

    公开(公告)日:1998-10-23

    申请号:JP4930398

    申请日:1998-03-02

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To issue an instruction to an execution unit even at the time of a continuous sequence and back-to-back in a random processing system by setting the valid bit of the target operand before the target operand of the instruction becomes usable. SOLUTION: The instruction is taken out from an instruction memory 100 and successively buffered in an instruction cache 101, then the instruction is decoded to a common internal instruction format and then, the instruction is transferred to a reservation station 103. In the reservation station 103, the instruction stands by until issuance to one of function units can be performed. In such a random processing system, the valid bit of the target operand is set before the target operand of the instruction becomes usable. A source operand is generated as the target operand of a preceding instruction and the instruction is immediately issued when the valid bit is set to the entire source operands.

    SWITCHING CONFIGURATION AND METHOD PROVIDED WITH SEPARATE OUTPUT BUFFER

    公开(公告)号:JP2002141948A

    公开(公告)日:2002-05-17

    申请号:JP2001281049

    申请日:2001-09-17

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a switching configuration to transport a data packet including data packet destination information and a payload to one output port or more. SOLUTION: Each input port 20 of a switching device 10 has an output buffer 35 that stores a payload of each data packet arrived in each input port 20 to its address. Furthermore, each input port 20 is provided with output queues whose number is the same as that of output ports 30. Each output queue stores addresses of each payload stored in the output buffer 35 and they are classified depending on data packet destination information. The stored payload can be sent to at least one of the output ports 30 under the use of the stored addresses at the point of time and pointed out by the addresses.

    3.
    发明专利
    未知

    公开(公告)号:DE60119866D1

    公开(公告)日:2006-06-29

    申请号:DE60119866

    申请日:2001-09-08

    Applicant: IBM

    Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.

    4.
    发明专利
    未知

    公开(公告)号:DE60119866T2

    公开(公告)日:2007-05-10

    申请号:DE60119866

    申请日:2001-09-08

    Applicant: IBM

    Abstract: The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.

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