中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.023 seconds)

    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS
    5.
    发明申请
    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 审中-公开
    用于沟槽电容器的碳纳米管导体

    公开(公告)号：WO2005069372A8

    公开(公告)日：2005-11-03

    申请号：PCT/US0340295

    申请日：2003-12-18

    Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

    Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

    Abstract translation: 沟槽型存储器件包括在衬底（100）中的沟槽，衬有沟槽的碳纳米管束（202）和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成沟槽衬里的开放柱状结构。 该装置通过在基底上提供碳纳米管催化剂结构并在基底中图案化沟槽而形成; 然后将碳纳米管向下生长到沟槽中以将沟槽与碳纳米管束对齐，之后用沟槽导体填充沟槽。

    VERTICALLY ISOLATED COMPLEMENTARY TRANSISTORS
    6.
    发明专利
    VERTICALLY ISOLATED COMPLEMENTARY TRANSISTORS 未知

    公开(公告)号：CA1208805A

    公开(公告)日：1986-07-29

    申请号：CA481991

    申请日：1985-05-21

    Applicant: IBM

    Inventor： ABERNATHEY JOHN R ,  KOBURGER CHARLES W III

    IPC: H01L27/08 ,  H01L21/20 ,  H01L21/225 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78

    Abstract: VERTICALLY ISOLATED COMPLEMENTARY TRANSISTORS A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.

    Memory structure and memory structure activation method
    7.
    发明专利
    Memory structure and memory structure activation method 审中-公开
    记忆结构和记忆结构激活方法

    公开(公告)号：JP2007158332A

    公开(公告)日：2007-06-21

    申请号：JP2006322502

    申请日：2006-11-29

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DAVID VACLAV HORAK ,  KOBURGER CHARLES W III ,  HAKEY MARK CHARLES ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU

    IPC: H01L27/10

    CPC classification number: G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure without gate leak current, and an activation method thereof. SOLUTION: The structure includes (a) a substrate, (b) first and second electrode regions 610, 1120 on the substrate, and (c) a third electrode region 1110 arranged between the first electrode region and the second electrode region. When a first write voltage potential is applied between the first electrode and the third electrode region, in response thereto, the third electrode region changes the shape of its own and then, when a predetermined read voltage potential is applied between the first electrode region and the third electrode region, in response thereto, a sense current flows between the first electrode region and the third electrode region. Further, when a second write voltage potential is applied between the second electrode region and the third electrode region, in response thereto, no sense current flows between the first electrode region and the third electrode region. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供没有栅极泄漏电流的存储单元结构及其激活方法。 解决方案：该结构包括（a）基板，（b）基板上的第一和第二电极区域610,1120，以及（c）布置在第一电极区域和第二电极区域之间的第三电极区域1110。 当在第一电极和第三电极区域之间施加第一写入电压电位时，响应于此，第三电极区域改变其本身的形状，然后当在第一电极区域和第二电极区域之间施加预定的读取电压电位时， 响应于此，感测电流在第一电极区域和第三电极区域之间流动。 此外，当在第二电极区域和第三电极区域之间施加第二写入电压电位时，响应于此，第一电极区域和第三电极区域之间没有感测电流流动。 版权所有（C）2007，JPO＆INPIT

    Movement of lens for immersion optical lithography
    9.
    发明专利
    Movement of lens for immersion optical lithography 有权
    镜头透镜光学平移运动

    公开(公告)号：JP2005197690A

    公开(公告)日：2005-07-21

    申请号：JP2004372593

    申请日：2004-12-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HAKEY MARK CHARLES ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: G03F7/20 ,  H01L21/027

    CPC classification number: G03F7/70341 ,  G03F7/70258

    Abstract: PROBLEM TO BE SOLVED: To provide a device which can minimize ripples and turbulence associated with the energy transfer between the movement of a lens and a liquid environment.
    SOLUTION: An apparatus for immersion optical lithography has a lens capable of relative movement in synchronization with horizontal motion of a semiconductor wafer in a liquid environment. The synchronized movements of the lens apparatus and the semiconductor wafer advantageously reduce turbulence and air bubbles associated with the liquid environment. The relative motions of the lens and the semiconductor wafer are performed almost simultaneously with a scanning process, resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption in the liquid environment.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种能够使与透镜的运动和液体环境之间的能量传递相关联的波纹和湍流最小化的装置。 解决方案：一种用于浸没光学光刻的设备具有能够在液体环境中与半导体晶片的水平运动同步的相对运动的透镜。 透镜装置和半导体晶片的同步运动有利地减少与液体环境相关联的湍流和气泡。 透镜和半导体晶片的相对运动几乎与扫描过程同时执行，从而在液体环境中产生最小的气泡，湍流和破坏的最佳图像分辨率。 版权所有（C）2005，JPO＆NCIPI

Patent Agency Ranking