Abstract:
PROBLEM TO BE SOLVED: To improve a manufacturing process of a three-dimensional integrated circuit chip or a wafer assembly, and further in detail, to make it possible to process chips in an arrayed state on a wafer before arranging the chips as stack. SOLUTION: The manufacture of the three-dimensional integrated circuit is disclosed wherein chip density can be made extremely high, and the wafer can be processed while keeping a planar form as a whole. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
Conductive sidewall spacer stractures are formed using a method tiiat patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
Abstract:
Non-volatile and radiation-hard switching and memory devices (225) using vertical nano-tubes (155) and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.
Abstract:
A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.
Abstract:
VERTICALLY ISOLATED COMPLEMENTARY TRANSISTORS A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.
Abstract:
PROBLEM TO BE SOLVED: To provide a memory cell structure without gate leak current, and an activation method thereof. SOLUTION: The structure includes (a) a substrate, (b) first and second electrode regions 610, 1120 on the substrate, and (c) a third electrode region 1110 arranged between the first electrode region and the second electrode region. When a first write voltage potential is applied between the first electrode and the third electrode region, in response thereto, the third electrode region changes the shape of its own and then, when a predetermined read voltage potential is applied between the first electrode region and the third electrode region, in response thereto, a sense current flows between the first electrode region and the third electrode region. Further, when a second write voltage potential is applied between the second electrode region and the third electrode region, in response thereto, no sense current flows between the first electrode region and the third electrode region. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a gain cell for a memory circuit, a memory circuit comprising multiple gain cells, and a method of producing such gain cells and memory circuits. SOLUTION: A memory gain cell 64 includes a storage capacitor 38, a write device which is electrically coupled to the storage capacitor for charging and discharging the storage capacitor, and a read device. The read device includes one or more semiconducting carbon nanotubes 50 each of which is electrically coupled between a source and a drain. A portion of each semiconducting carbon nanotube is gated by a read gate 60 and the storage capacitor, thereby regulating a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a device which can minimize ripples and turbulence associated with the energy transfer between the movement of a lens and a liquid environment. SOLUTION: An apparatus for immersion optical lithography has a lens capable of relative movement in synchronization with horizontal motion of a semiconductor wafer in a liquid environment. The synchronized movements of the lens apparatus and the semiconductor wafer advantageously reduce turbulence and air bubbles associated with the liquid environment. The relative motions of the lens and the semiconductor wafer are performed almost simultaneously with a scanning process, resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption in the liquid environment. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a method for synthesizing carbon nanotubes and a structure formed by the carbon nanotubes. SOLUTION: A method for synthesizing the carbon nanotubes includes a step for forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, a step for interrupting nanotube synthesis, a step for mounting a free end of each carbon nanotube onto a second substrate, and a step for removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded. COPYRIGHT: (C)2005,JPO&NCIPI