公开(公告)号：EP2742385A4

公开(公告)日：2014-06-18

申请号：EP12822200

申请日：2012-08-10

Applicant: IBM

Inventor： CHEN KUANG-JUNG ,  HOLMES STEVEN J ,  HUANG WU-SONG ,  LIU SEN

IPC: G03F7/004 ,  C09D133/04 ,  C09J133/14 ,  G03F7/038 ,  G03F7/039 ,  G03F7/09 ,  G03F7/095

CPC classification number: G03F7/0382 ,  C09J133/14 ,  G03F7/091 ,  G03F7/094 ,  G03F7/095

公开(公告)号：EP1849187A4

公开(公告)日：2010-11-17

申请号：EP06717977

申请日：2006-01-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

公开(公告)号：EP1430536A4

公开(公告)日：2006-04-26

申请号：EP02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

公开(公告)号：JPH113965A

公开(公告)日：1999-01-06

申请号：JP10935898

申请日：1998-04-20

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  FERENCE THOMAS G ,  HOLMES STEVEN J

IPC: H01L23/52 ,  H01L23/48 ,  H01L25/065

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which a wire lead is not covered and a chip access face is insulated. SOLUTION: The semiconductor device has a conductive lead 25 which is positioned inside of a first insulating material 22 and a tip end of which is exposed. In this case, the first insulating material 22 is alternately provided between first and second insulated integrated circuit chips 10 and 16. The first insulating material 22 is etched to form a recess therein and thereafter, a second insulating material 34 is provided on an access face 30 of the first and second chips 10 and 16 and on an inside face of the recess. Next a tip end 25 of the wire lead is exposed by chemical-mechanical polishing or by a wet-etching/ developing process.

公开(公告)号：JP2007142416A

公开(公告)日：2007-06-07

申请号：JP2006308607

申请日：2006-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOBURGER CHARLES W III ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  DAVID VACLAV HORAK

IPC: H01L31/02

CPC classification number: H01L31/101 ,  H01L27/14647 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor and a method of forming the optical sensor.
SOLUTION: The optical sensor structure includes (a) a semiconductor substrate, (b) a first, a second, a third, a fourth, a fifth, and a sixth electrodes and (c) a first, a second, and a third semiconductor regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is deeper than the second depth, and the second depth is deeper than the third depth. The first semiconductor region, the second semiconductor region, and the third semiconductor region are laid out between the first electrode and the fourth electrode, between the second electrode and the fifth electrode, and between the third electrode and the sixth electrodes, respectively, and are in contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first semiconductor region, the second semiconductor region, and the third semiconductor region come into contact with each other.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种光学传感器和形成光学传感器的方法。 解决方案：光学传感器结构包括（a）半导体衬底，（b）第一，第二，第三，第四，第五和第六电极和（c）第一，第二和第 第三半导体区域。 第一和第四电极处于第一深度。 第二和第五电极处于第二深度。 第三和第六电极处于第三深度。 第一深度比第二深度深，第二深度比第三深度深。 第一半导体区域，第二半导体区域和第三半导体区域分别布置在第一电极和第四电极之间，第二电极和第五电极之间以及第三电极和第六电极之间，并且分别是 分别与第一和第四电极，第二和第五电极以及第三和第六电极接触。 第一半导体区域，第二半导体区域和第三半导体区域彼此接触。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2008306204A

公开(公告)日：2008-12-18

申请号：JP2008199617

申请日：2008-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MARK C HEIKEE ,  HOLMES STEVEN J ,  DAVID V HOLICK ,  WILLIAM H MA

IPC: G03F7/004 ,  H01L21/8242 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085 ,  Y10S430/168 ,  Y10T428/24355 ,  Y10T428/24628

Abstract: PROBLEM TO BE SOLVED: To provide an easy method for manufacturing a high capacitance storage node structure for DRAM, and the like. SOLUTION: A high-capacitance storage node structure is produced in a substrate 10, by patterning a hybrid resist 12, to produce both negative tone resist regions 16 and positive tone resist regions 18 in the exposed region 14. After the removal of the positive tone resist regions 18, the substrate 10 is etched by using the unexposed hybrid resist 12 and negative tone resist regions 16 as a mask. This produces a trench 22 in the substrate 10 with a centrally located, upwardly projecting protrusion 24. A capacitor 26 is then produced by coating the sidewalls of the trench 22 and protrusion 24 with a dielectric 28 and filling the trench 22 with a conductive material 30, such as polysilicon. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于制造用于DRAM的高电容存储节点结构的简单方法等。 解决方案：通过图案化混合抗蚀剂12，在衬底10中产生高电容存储节点结构，以在暴露区域14中产生负色调抗蚀剂区域16和正色调抗蚀剂区域18。 通过使用未曝光的混合抗蚀剂12和负色调抗蚀剂区域16作为掩模来蚀刻正色调抗蚀剂区域18，衬底10。 这在基板10中产生具有中心定位的向上突出的突起24的沟槽22.然后通过用电介质28涂覆沟槽22和突起24的侧壁并用导电材料30填充沟槽22来产生电容器26 ，如多晶硅。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006148093A

公开(公告)日：2006-06-08

申请号：JP2005319160

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  MARK C HEIKY ,  FURUKAWA TOSHIHARU ,  DAVID V HOLLACK

IPC: H01L21/027 ,  G03F7/20

CPC classification number: G03F7/70341 ,  G03F7/70925

Abstract: PROBLEM TO BE SOLVED: To remove smearing residue in an immersion lithography system. SOLUTION: The equipment for cleaning a semiconductor substrate comprises a chamber having an upper portion, a sidewall and a bottom opening where the upper portion is transparent to light of selected wavelength, an inlet and an outlet provided in the sidewall of the chamber, a plate extending outward from the bottom edge of the chamber, a set of concentric grooves formed in the bottom face of the plate and centering on the chamber, a means for applying vacuum to first and fourth grooves closest to the bottom opening of the chamber in the set of grooves, a means for supplying inert gas or vapor mixture of inert gas and solvent to a second groove between the first and fourth grooves and a fifth groove on the outside of the fourth groove in the set of grooves, and a means for supplying cleaning fluid to a third groove between the second and fourth grooves in the set of grooves. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：去除浸没式光刻系统中的污渍残留物。 解决方案：用于清洁半导体衬底的设备包括具有上部，侧壁和底部开口的室，其中上部对于所选波长的光是透明的，入口和出口设置在室的侧壁中 ，从所述室的底部边缘向外延伸的板，形成在所述板的底面中并且以所述室为中心的一组同心槽，用于对最靠近所述室的底部开口的第一和第四凹槽施加真空的装置 在一组凹槽中，用于将惰性气体或惰性气体和溶剂的惰性气体或蒸汽混合物供应到第一和第四凹槽之间的第二凹槽和该组凹槽中的第四凹槽的外侧上的第五凹槽的装置， 用于将清洁流体供应到所述一组凹槽中的第二和第四凹槽之间的第三凹槽。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO03019671A3

公开(公告)日：2003-04-10

申请号：PCT/US0228265

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

Abstract translation: 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻形成的半导体柱（2910）的相对侧的潜在独立的栅极结构（3230）。 栅极结构由绝缘材料（2620）包围，其被选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，将一个触点（3820）制成在支柱的下端。 柱的上端由盖​​（2730）和选择性可蚀刻材料的侧壁覆盖，使得栅极和源极连接开口（3720,3620）也可以通过具有良好配准公差的选择性蚀刻制成。

公开(公告)号：JP2006338002A

公开(公告)日：2006-12-14

申请号：JP2006142379

申请日：2006-05-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CORLISS DANIEL A ,  GIL DARIO ,  GOLDFARB DARIO L ,  HOLMES STEVEN J ,  HORAK DAVID VACLAV ,  KIMMEL KURT R ,  PETRILLO KAREN E ,  SHNEYDER DMITRIY I

IPC: G03F7/11 ,  H01L21/027

CPC classification number: G03F7/2041 ,  G03F7/11 ,  Y10S430/162

Abstract: PROBLEM TO BE SOLVED: To prevent interaction between a photoresist layer and an immersion fluid in a immersion lithography system and to prevent contaminants in the immersion fluid from contaminating an integrated circuit being fabricated.
SOLUTION: The method for forming an image in a photoresist layer includes: a step of providing a substrate; a step (S12) of forming a photoresist layer over the substrate; a step (S16) of forming a contamination gettering topcoat layer over the photoresist layer, the contamination gettering topcoat layer including contains one or more polymers and one or more cation complexing agents; a step of exposing the photoresist layer to actinic radiation; and a step of removing an exposed region of the photoresist layer or an unexposed region of the photoresist layer. The contamination gettering topcoat layer includes one or more polymers, one or more cation complexing agents, and a casting solvent.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了防止浸没式光刻系统中的光致抗蚀剂层和浸没流体之间的相互作用并且防止浸没流体中的污染物污染正在制造的集成电路。 解决方案：在光致抗蚀剂层中形成图像的方法包括：提供基板的步骤; 在衬底上形成光致抗蚀剂层的步骤（S12）; 在光致抗蚀剂层上形成污染吸气外涂层的步骤（S16），包含吸污顶层的污染物包含一种或多种聚合物和一种或多种阳离子络合剂; 将光致抗蚀剂层暴露于光化辐射的步骤; 以及除去光致抗蚀剂层的曝光区域或光致抗蚀剂层的未曝光区域的步骤。 污染吸附顶涂层包括一种或多种聚合物，一种或多种阳离子络合剂和流延溶剂。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006148092A

公开(公告)日：2006-06-08

申请号：JP2005319158

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  CORLISS DANIEL A ,  DAVID V HOLLACK ,  KOBURGER CHARLES W

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/683

CPC classification number: G03F7/707 ,  G03F7/70341 ,  G03F7/70808

Abstract: PROBLEM TO BE SOLVED: To provide a method and equipment in which the possibility of bringing immersion fluid from a clearance or other portion of a chuck onto the surface of a photoresist layer on a wafer is not high. SOLUTION: Equipment for holding a wafer and a method for immersion lithography. The equipment comprises a wafer chuck having a central circular vacuum platen, an outside region, and a circular groove centering on the vacuum platen. Upper surface of the vacuum platen is recessed below the upper surface of the outside region, and the layer surface of the groove is recessed below the upper part of the vacuum platen, one or more suction ports are provided in the lower surface of the groove, and a hollow toroidal bladder capable of expansion or contraction is arranged in the groove. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种方法和设备，其中将来自夹盘的间隙或其他部分的浸没流体的可能性提供到晶片上的光致抗蚀剂层的表面上的可能性不高。

解决方案：用于保持晶片的设备和浸没式光刻方法。 该设备包括具有中心圆形真空压板，外部区域和以真空压板为中心的圆形槽的晶片卡盘。 真空压板的上表面在外部区域的上表面下方凹陷，并且凹槽的表面凹陷在真空压板的上部下方，在凹槽的下表面中设置一个或多个吸入口， 并且在槽中布置能够膨胀或收缩的空心环形囊。 版权所有（C）2006，JPO＆NCIPI