中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.017 seconds)

    3.
    发明专利
    未知

    公开(公告)号：DE69218076D1

    公开(公告)日：1997-04-17

    申请号：DE69218076

    申请日：1992-08-10

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

    IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.

    4.
    发明专利
    未知

    公开(公告)号：DE2534397A1

    公开(公告)日：1976-04-22

    申请号：DE2534397

    申请日：1975-08-01

    Applicant: IBM

    Inventor： ALBERTS GENE STODDARD ,  FARRAR PAUL ALDEN ,  HALLEN ROBERT LEE

    IPC: G11C17/00 ,  G11C11/24 ,  G11C11/404 ,  H01L21/00 ,  H01L23/29 ,  H01L23/525 ,  H01L27/10 ,  H01L21/90

    Abstract: Disclosed is an improved method for manufacturing semiconductor integrated circuitry whereby interconnection pad limiting metallurgy and read only fusible link memory structure is simultaneously formed by first blank depositing a composite metal film followed by in situ forming pad metallurgy and said read only link structure utilizing photoresist and etch techniques. Said read only memory link structure is utilized for directing the use of redundant lines in place of defective array bits.

    5.
    发明专利
    未知

    公开(公告)号：DE2228678A1

    公开(公告)日：1973-01-18

    申请号：DE2228678

    申请日：1972-06-13

    Applicant: IBM

    Inventor： FARRAR PAUL ALDEN

    IPC: H01L21/00 ,  H01L23/532 ,  H01L7/02

    Abstract: An electrical interconnection contact structure including a layer containing a major proportion of an intermetallic compound contacting the surface of an integrated circuit device. The intermetallic layer is covered by a layer of conductive alloy which includes a major proportion of a solid solution of the same chemical elements as the intermetallic compound. One of the chemical elements is preferred to be an electromigration preventing dopant. Two methods of creating such a contact structure are disclosed including a sandwich technique where a layer of a first element and a layer of a second element form the intermetallic compound and a co-deposition technique where the first and second elements are co-deposited as the intermetallic compound. An alternative embodiment includes causing the intermetallic layer to spheroidize after exposure to high temperature stress allowing the major ingredient of the overlying layer to contact the semiconductor surface between spheroids. The invention provides an effective method of controlling spiking of shallow semiconductor junctions while improving the electromigration characteristics of the conductive member.

    6.
    发明专利
    未知

    公开(公告)号：DE69218076T2

    公开(公告)日：1997-09-18

    申请号：DE69218076

    申请日：1992-08-10

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

    IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.

    8.
    发明专利
    未知

    公开(公告)号：DE2440481A1

    公开(公告)日：1975-04-24

    申请号：DE2440481

    申请日：1974-08-23

    Applicant: IBM

    Inventor： COOK HERBERT CARL ,  FARRAR PAUL ALDEN ,  HALLEN ROBERT LEE

    IPC: H05K3/24 ,  H01B1/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/52 ,  H01L23/532 ,  H05K3/38 ,  H05K3/46 ,  H05K3/16

    Abstract: Disclosed is a method for the manufacture of composite thin films useful among other applications as electronic microcircuit interconnections, fuses, and contacts, terminal pads and voltage distribution ring metallurgy comprising in carrying out an integral circuit fabrication process the steps of first depositing a barrier layer of antidiffusion material, such as chromium, followed by superimposing thereon a film of highly conductive metals susceptible to corrosion and followed by the deposition of a highly corrosive resistant metal film. A subtractive etch pattern is formed in the composite metal film followed by heating the structure to an elevated temperature for a predetermined period of time so that the uppermost layer of the composite flows by diffusion over the edge section to protect the conductive metal film from corrosive effects.

Patent Agency Ranking