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    Vertical DRAM cell with TFT over trench capacitor
    1.
    发明授权
    Vertical DRAM cell with TFT over trench capacitor 失效
    具有TFT沟槽电容器的垂直DRAM单元

    公开(公告)号：US6373091B2

    公开(公告)日：2002-04-16

    申请号：US76556101

    申请日：2001-01-19

    Applicant: IBM

    Inventor： HORAK DAVID VACLAV ,  MOHLER RICK LAWRENCE ,  STARKEY JR GORDEN SETH

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

    Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a method of manufacturing the same is provided.

    Abstract translation: 一种记忆单元，包括具有顶表面的基底; 电容器垂直延伸到基板中，用于存储表示基准的电压，所述电容器占据几何形状的水平面积; 晶体管，形成在电容器上方并且占据基本上等于几何形状水平面积的水平面积，并且具有垂直器件深度，用于响应于控制信号与电容器建立电连接，用于读取和写入 所述电容器，其中所述晶体管包括形成在所述水平装置区域的周边附近并具有大约等于垂直装置深度的垂直深度的栅极; 栅极内表面上的氧化物层; 形成在所述氧化物层内部的导电体，所述导电体具有顶表面和底表面以及垂直深度近似等于垂直装置深度; 并且在顶部和底部表面附近的主体中的扩散区域及其制造方法。

    5.
    发明专利
    未知

    公开(公告)号：DE3580335D1

    公开(公告)日：1990-12-06

    申请号：DE3580335

    申请日：1985-08-20

    Applicant: IBM

    Inventor： HORR ROBERT ARTHUR ,  MOHLER RICK LAWRENCE

    IPC: H01L21/033 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/82 ,  H01L21/00

    Abstract: A process is provided for making semiconductor structures. such as CMOS structures, which includes forming on a surface of a semiconductor body (12) a layer from a material which is impervious to oxygen diffusion therethrough and patterning this layer to define the position of both the active and field isolation regions by partially removing this layer from the areas where the field isolation regions are to be formed. This oxygen impervious layer may be a dual dielectric structure consisting of a layer of silicon dioxide (14) adjoinmg the semiconductor body and a layer of silicon nitride (16) adjoining the silicon dioxide. The resulting structure includes an oxygen impervious layer (16b) which is used both for protecting all underlying oxidizing regions from oxidation and for defining the position of the active regions of the structure.

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