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    Method of precharging and precharge circuit for dynamic cascode voltage switch logic.
    1.
    发明公开
    Method of precharging and precharge circuit for dynamic cascode voltage switch logic. 失效
    方法和Schattungsanordnung预充电动态共源共栅逻辑电路。

    公开(公告)号：EP0206462A2

    公开(公告)日：1986-12-30

    申请号：EP86302860

    申请日：1986-04-16

    Applicant: IBM

    Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

    IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

    CPC classification number: H03K19/1738

    Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

    5.
    发明专利
    未知

    公开(公告)号：DE3682121D1

    公开(公告)日：1991-11-28

    申请号：DE3682121

    申请日：1986-04-16

    Applicant: IBM

    Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

    IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

    Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

    6.
    发明专利
    未知

    公开(公告)号：DE3483495D1

    公开(公告)日：1990-12-06

    申请号：DE3483495

    申请日：1984-04-25

    Applicant: IBM

    Inventor： DILL FREDERICK HAYES ,  LING DANIEL TAJEN ,  MATICK RICHARD EDWARD ,  MCBRIDE DENNIS JAY

    IPC: G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G06F13/38 ,  G06F15/167 ,  G06F15/16

    Abstract: A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer means connected in between the first and second bit arrays of each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A control means is located on each chip and connected to the first and second memory arrays and the M bit buffer means for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.

    8.
    发明专利
    未知

    公开(公告)号：DE3585932D1

    公开(公告)日：1992-06-04

    申请号：DE3585932

    申请日：1985-05-10

    Applicant: IBM

    Inventor： CHUNG PAUL WING-SHING ,  MATICK RICHARD EDWARD ,  LING DANIEL TAJEN

    IPC: G11C11/401 ,  G06F12/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/00 ,  G11C11/409

    Abstract: A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.

    CIRCUITS FOR ACCESSING A VARIABLE WIDTH DATA BUS WITH A VARIABLE WIDTH DATA FIELD
    9.
    发明专利
    CIRCUITS FOR ACCESSING A VARIABLE WIDTH DATA BUS WITH A VARIABLE WIDTH DATA FIELD 未知

    公开(公告)号：DE3380572D1

    公开(公告)日：1989-10-19

    申请号：DE3380572

    申请日：1983-06-01

    Applicant: IBM

    Inventor： DILL FREDERICK HAYES ,  LING DANIEL TAJEN ,  MATICK RICHARD EDWARD ,  MCBRIDE DENNIS JAY

    IPC: G06F13/36 ,  G06F5/00 ,  G06F5/01 ,  G06F7/76 ,  G06F13/40

    Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N c and a data field of N f , the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. Structure includes a modulo N c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N c . A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.

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