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    Vertical DRAM cell with TFT over trench capacitor
    1.
    发明授权
    Vertical DRAM cell with TFT over trench capacitor 失效
    具有TFT沟槽电容器的垂直DRAM单元

    公开(公告)号：US6373091B2

    公开(公告)日：2002-04-16

    申请号：US76556101

    申请日：2001-01-19

    Applicant: IBM

    Inventor： HORAK DAVID VACLAV ,  MOHLER RICK LAWRENCE ,  STARKEY JR GORDEN SETH

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

    Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a method of manufacturing the same is provided.

    Abstract translation: 一种记忆单元，包括具有顶表面的基底; 电容器垂直延伸到基板中，用于存储表示基准的电压，所述电容器占据几何形状的水平面积; 晶体管，形成在电容器上方并且占据基本上等于几何形状水平面积的水平面积，并且具有垂直器件深度，用于响应于控制信号与电容器建立电连接，用于读取和写入 所述电容器，其中所述晶体管包括形成在所述水平装置区域的周边附近并具有大约等于垂直装置深度的垂直深度的栅极; 栅极内表面上的氧化物层; 形成在所述氧化物层内部的导电体，所述导电体具有顶表面和底表面以及垂直深度近似等于垂直装置深度; 并且在顶部和底部表面附近的主体中的扩散区域及其制造方法。

    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD
    3.
    发明专利
    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD 失效

    公开(公告)号：JPH11289069A

    公开(公告)日：1999-10-19

    申请号：JP1527799

    申请日：1999-01-25

    Applicant: IBM

    Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

    IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

    Wrap-around type gate field effect transistor
    5.
    发明专利
    Wrap-around type gate field effect transistor 有权
    缠绕型门控场效应晶体管

    公开(公告)号：JP2005175485A

    公开(公告)日：2005-06-30

    申请号：JP2004353618

    申请日：2004-12-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    Abstract: PROBLEM TO BE SOLVED: To provide a gate formation method capable of controlling the gate length of a self-aligned wrap-around type field effect transistor easily, accurately, and securely. SOLUTION: A reference edge in the vertical direction is determined by forming a cavity in an silicon on insulator (SOI) structure having an embedded silicon island 108. In order to securely carry out an etch back, the reference edge is used in two etch back stages. In the first etch back, part of oxide layer corresponding to a first distance is removed and then, a gate conductive material is applied thereon. In the second etch back, part of the gate conductive material corresponding to a second distance is removed. The difference between the first distance and the second distance determines the final gate length of a device. After the oxide layer is peeled off and removed, gate electrodes 904 and 906 in the vertical direction surrounding the embedded silicon island 108 appear at all four sides. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够容易，准确且可靠地控制自对置环绕型场效应晶体管的栅极长度的栅极形成方法。 解决方案：通过在具有嵌入硅岛108的绝缘体上硅（SOI）结构中形成空腔来确定垂直方向上的参考边缘。为了可靠地执行回蚀刻，参考边缘用于 两个回蚀阶段。 在第一回蚀刻中，除去对应于第一距离的部分氧化物层，然后在其上施加栅极导电材料。 在第二次回蚀时，去除对应于第二距离的栅极导电材料的一部分。 第一距离和第二距离之间的差值决定了装置的最终栅极长度。 在去除和除去氧化物层之后，围绕嵌入硅岛108的垂直方向的栅电极904和906出现在所有四个侧面。 版权所有（C）2005，JPO＆NCIPI

    Method for forming image in resist, topcoat layer material (immersion lithography contamination gettering layer)
    8.
    发明专利
    Method for forming image in resist, topcoat layer material (immersion lithography contamination gettering layer) 有权
    用于形成耐蚀图像的方法，顶层材料（渗透层析污染捕获层）

    公开(公告)号：JP2006338002A

    公开(公告)日：2006-12-14

    申请号：JP2006142379

    申请日：2006-05-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CORLISS DANIEL A ,  GIL DARIO ,  GOLDFARB DARIO L ,  HOLMES STEVEN J ,  HORAK DAVID VACLAV ,  KIMMEL KURT R ,  PETRILLO KAREN E ,  SHNEYDER DMITRIY I

    IPC: G03F7/11 ,  H01L21/027

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  Y10S430/162

    Abstract: PROBLEM TO BE SOLVED: To prevent interaction between a photoresist layer and an immersion fluid in a immersion lithography system and to prevent contaminants in the immersion fluid from contaminating an integrated circuit being fabricated.
    SOLUTION: The method for forming an image in a photoresist layer includes: a step of providing a substrate; a step (S12) of forming a photoresist layer over the substrate; a step (S16) of forming a contamination gettering topcoat layer over the photoresist layer, the contamination gettering topcoat layer including contains one or more polymers and one or more cation complexing agents; a step of exposing the photoresist layer to actinic radiation; and a step of removing an exposed region of the photoresist layer or an unexposed region of the photoresist layer. The contamination gettering topcoat layer includes one or more polymers, one or more cation complexing agents, and a casting solvent.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了防止浸没式光刻系统中的光致抗蚀剂层和浸没流体之间的相互作用并且防止浸没流体中的污染物污染正在制造的集成电路。 解决方案：在光致抗蚀剂层中形成图像的方法包括：提供基板的步骤; 在衬底上形成光致抗蚀剂层的步骤（S12）; 在光致抗蚀剂层上形成污染吸气外涂层的步骤（S16），包含吸污顶层的污染物包含一种或多种聚合物和一种或多种阳离子络合剂; 将光致抗蚀剂层暴露于光化辐射的步骤; 以及除去光致抗蚀剂层的曝光区域或光致抗蚀剂层的未曝光区域的步骤。 污染吸附顶涂层包括一种或多种聚合物，一种或多种阳离子络合剂和流延溶剂。 版权所有（C）2007，JPO＆INPIT

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