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    Sublithographic fuses using a phase shift mask
    1.
    发明授权
    Sublithographic fuses using a phase shift mask 失效
    使用相移掩模的亚光刻保险丝

    公开(公告)号：US6278171B2

    公开(公告)日：2001-08-21

    申请号：US73466800

    申请日：2000-12-13

    Applicant: IBM

    Inventor： ARNDT KENNETH C ,  HSU LOUIS L ,  MANDELMAN JACK A ,  MULLER K PAUL

    IPC: H01L23/525 ,  H01L29/00

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

    Abstract translation: 用于形成诸如熔丝结构的互连布线结构的方法包括使用相移掩模（具有垂直侧壁倾斜的侧壁和水平表面的开口）在绝缘层中形成开口，在开口中沉积导电材料并除去 来自倾斜侧壁和水平表面的导电材料，其中导电材料作为熔丝链保持在垂直侧壁上。

    DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
    2.
    发明申请
    DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION 审中-公开
    双栅极晶体管和制造方法

    公开(公告)号：WO03001604A2

    公开(公告)日：2003-01-03

    申请号：PCT/EP0206202

    申请日：2002-06-06

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

    CPC classification number: H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

    Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.

    Abstract translation: 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

    Integrated circuit optimization method (opc trimming for improving performance)
    4.
    发明专利
    Integrated circuit optimization method (opc trimming for improving performance) 有权
    集成电路优化方法（OPC TRIMMING FOR IMPROVE PERFORMANCE）

    公开(公告)号：JP2007133394A

    公开(公告)日：2007-05-31

    申请号：JP2006294934

    申请日：2006-10-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CULP JAMES A ,  LARS W LIEBMAN ,  MALIK RAJEEV ,  MULLER K PAUL ,  NARASIMHA SHREESH ,  RUNYON STEPHEN L ,  WILLIAMS PATRICK M

    IPC: G03F1/08 ,  H01L21/82

    CPC classification number: G06F17/5068

    Abstract: PROBLEM TO BE SOLVED: To provide a method for improving the yield, performance and timing of an integrated circuit. SOLUTION: An iterative timing analysis is performed analytically before a chip is fabricated, based on a technique that uses optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time-sensitive devices. An additional mask is used as a selective trim, to form shortened gate lengths or wider metal lines for selected predetermined transistors, affecting threshold voltages and RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. This analysis methodology is repeated as often as needed, to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants, until manufacturing limits are reached. A mask is made for the selected critical devices by using OPC techniques. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于提高集成电路的产量，性能和时序的方法。 解决方案：基于使用光学邻近校正技术缩短栅极长度和调整关键时间敏感器件的金属线宽度和接近距离的技术，在芯片制造之前分析地执行迭代时序分析。 使用附加掩模作为选择性修整，以形成选定的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 该分析方法根据需要经常重复，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为选定的关键设备制作掩码。 版权所有（C）2007，JPO＆INPIT

    5.
    发明专利
    未知

    公开(公告)号：DE69939573D1

    公开(公告)日：2008-10-30

    申请号：DE69939573

    申请日：1999-11-16

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： FLIETNER BERTRAND ,  MULLER K PAUL

    IPC: G05B19/00 ,  H01L21/66 ,  G05D23/00 ,  H01L23/544

    Abstract: A measurement device for in-situ measurement of processing parameters, in accordance with the present invention, includes a semiconductor wafer having at least one processed chip formed thereon. The processed chip further includes at least one sensor for measuring process parameters. A memory storage device for storing the process parameters as the process parameters are measured by the at least one sensor is also included. A timing device is provided for tracking the process parameters as a function of time, and a power supply is included for providing power to the at least one sensor, the memory storage device and the timing device. Also, a method is described for making measurements with the measurement device.

    6.
    发明专利
    未知

    公开(公告)号：DE10296953B4

    公开(公告)日：2010-04-08

    申请号：DE10296953

    申请日：2002-06-06

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

    IPC: H01L21/283 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

    Cooling system control and servicing based on time-based variation of an operational variable
    8.
    发明专利
    Cooling system control and servicing based on time-based variation of an operational variable 未知

    公开(公告)号：GB2515682A

    公开(公告)日：2014-12-31

    申请号：GB201416843

    申请日：2013-03-06

    Applicant: IBM

    Inventor： MULLER K PAUL ,  VOGEL ANDREW HAROLD ,  KEARNEY DANIEL JAMES ,  YASHCHIN EMMANUEL ,  LEVESQUE REJEAN PAUL

    IPC: H05K7/20 ,  F25B5/02 ,  F25B49/02

    Abstract: Automated control of a cooling system cooling at least one electronic component is provided. The control includes monitoring over a period of time variation of an operational variable of the cooling system or of the at least one electronic component, and based, at least in part, on variation of the operational variable over the period of time, automatically determining whether to adjust control of the cooling system to limit variation of the operational variable. In one implementation, depending on the variation of the operational variable, and whether control of the cooling system has been previously adjusted, the method may further include automatically determining a probability of fail or an expected residual life of the cooling system, and responsive to the predicted probability of fail exceeding a first acceptable threshold or the expected residual life being below a second acceptable threshold, automatically scheduling for a cooling system repair or replacement.

    9.
    发明专利
    未知

    公开(公告)号：DE10296953T5

    公开(公告)日：2004-04-29

    申请号：DE10296953

    申请日：2002-06-06

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

    Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

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