公开(公告)号：GB2595160A

公开(公告)日：2021-11-17

申请号：GB202111646

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS LOUBET

IPC: H01L21/02 ,  H01L29/786

Abstract: A technique for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. A non-planar channel region is formed having a first semiconductor layer (208), a second semiconductor layer (206), and a fin-shaped bridge layer between the first semiconductor layer (208) and the second semiconductor layer (206). Forming the non-planar channel region can include forming a nanosheet stack over a substrate (204), forming a trench (502) by removing a portion of the nanosheet stack, and forming a third semiconductor layer (602) in the trench (502). Outer surfaces of the first semiconductor layer (208), the second semiconductor layer (206), and the fin-shaped bridge region define an effective channel width of the non-planar channel region.