中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.019 seconds)

    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation
    1.
    发明专利
    CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation 未知

    公开(公告)号：GB2631071B

    公开(公告)日：2025-04-16

    申请号：GB202414743

    申请日：2023-03-23

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

    IPC: H10D62/13 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

    Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

    Nanosheet transistor with self-aligned dielectric pillar
    2.
    发明专利
    Nanosheet transistor with self-aligned dielectric pillar 未知

    公开(公告)号：GB2607481A

    公开(公告)日：2022-12-07

    申请号：GB202211293

    申请日：2020-12-23

    Applicant: IBM

    Inventor： RUILONG XIE ,  KANGGUO CHENG ,  JULIEN FROUGIER

    IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088

    Abstract: A semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance are provided. A nanosheet stack (206) is formed over a substrate (204). A dielectric pillar (402) is positioned adjacent to the nanosheet stack (206) and on a shallow trench isolation region (212) of the substrate (204). The nanosheet stack (206) is recessed to expose a surface of the shallow trench isolation region (212) and a source or drain (S/D) region (602) is formed on the exposed surface of the shallow trench isolation region (212). A contact trench (802) is formed that exposes a surface of the S/D region (602) and a surface of the dielectric pillar (402).

    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
    4.
    发明专利
    Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions 未知

    公开(公告)号：GB2595160A

    公开(公告)日：2021-11-17

    申请号：GB202111646

    申请日：2020-02-24

    Applicant: IBM

    Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS LOUBET

    IPC: H01L21/02 ,  H01L29/786

    Abstract: A technique for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. A non-planar channel region is formed having a first semiconductor layer (208), a second semiconductor layer (206), and a fin-shaped bridge layer between the first semiconductor layer (208) and the second semiconductor layer (206). Forming the non-planar channel region can include forming a nanosheet stack over a substrate (204), forming a trench (502) by removing a portion of the nanosheet stack, and forming a third semiconductor layer (602) in the trench (502). Outer surfaces of the first semiconductor layer (208), the second semiconductor layer (206), and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

    Structure and method to fabricate resistive memory with vertical pre-determined filament
    6.
    发明专利
    Structure and method to fabricate resistive memory with vertical pre-determined filament 未知

    公开(公告)号：GB2604518A

    公开(公告)日：2022-09-07

    申请号：GB202207339

    申请日：2020-10-12

    Applicant: IBM

    Inventor： CHANRO PARK ,  CHENG KANGGUO ,  RUILONG XIE ,  CHOONGHYUN LEE

    IPC: H01L27/105

    Abstract: A semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming by atomic layer deposition in the cell contact hole a second dielectric layer including a seam; forming a bottom electrode within the cavity and in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and in contact with the second dielectric layer and the seam.

    High density reram integration with interconnect
    7.
    发明专利
    High density reram integration with interconnect 未知

    公开(公告)号：GB2603591A

    公开(公告)日：2022-08-10

    申请号：GB202116915

    申请日：2021-11-24

    Applicant: IBM

    Inventor： TAKASHI ANDO ,  ALEXANDER REZNICEK ,  POUYA HASHEMI ,  RUILONG XIE

    IPC: H01L45/00 ,  G11C13/00

    Abstract: A cross-bar ReRAM comprising: a substrate 205; a plurality of first columns extending from the substrate and containing a ReRAM stack 220, 225, 230, 226, 221; a plurality of second columns 250, 255 extending perpendicular to the first columns, and located on top of the first columns such that they cross over the first columns; and, a dielectric layer 245 filling the space between the first and the second columns, wherein the dielectric layer is in direct contact with a sidewall of each layer of the ReRAM stack. ReRAM stack layers 220 & 221 may comprise TaN, layers 225 & 226 may comprise TiN and layer 230 may comprise HfO2. Each column may comprise a metal liner with a metal layer formed thereon. The ReRAM stack may be in direct contact with the second column. A logic circuit may be formed at the same time as the ReRAM array.

    Nanosheet transistors with wrap around contact
    8.
    发明专利
    Nanosheet transistors with wrap around contact 未知

    公开(公告)号：GB2603283A

    公开(公告)日：2022-08-03

    申请号：GB202117763

    申请日：2021-12-09

    Applicant: IBM

    Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: A method including: forming a source/drain on an exposed portion of a semiconductor layer 123,126 of a layered nanosheet; forming a sacrificial material on the source/drain; forming a dielectric layer 205 covering the sacrificial material; and replacing the sacrificial material with a contact liner 240. Also disclosed is a semiconductor device including: a first gate nanosheet stack and second gate nanosheet stack; a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack; a source/drain dielectric 205 located between the first source/drain and the second source/drain; and a contact liner 240 in contact with the first source/drain, the second source/drain and the source/drain dielectric 205. Further disclosed is the method of forming the semiconductor device using the above method.

    Nanosheet transistor with self-aligned dielectric pillar
    10.
    发明专利
    Nanosheet transistor with self-aligned dielectric pillar 未知

    公开(公告)号：GB2607481B

    公开(公告)日：2025-02-05

    申请号：GB202211293

    申请日：2020-12-23

    Applicant: IBM

    Inventor： RUILONG XIE ,  KANGGUO CHENG ,  JULIEN FROUGIER

    IPC: H01L21/768 ,  H01L23/485 ,  H10D30/43 ,  H10D30/67 ,  H10D48/36 ,  H10D62/10 ,  H10D62/13 ,  H10D64/27 ,  H10D84/03 ,  H10D84/83

    Abstract: Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.

Patent Agency Ranking