公开(公告)号：GB2631071B

公开(公告)日：2025-04-16

申请号：GB202414743

申请日：2023-03-23

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

IPC: H10D62/13 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

公开(公告)号：GB2595160A

公开(公告)日：2021-11-17

申请号：GB202111646

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS LOUBET

IPC: H01L21/02 ,  H01L29/786

Abstract: A technique for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. A non-planar channel region is formed having a first semiconductor layer (208), a second semiconductor layer (206), and a fin-shaped bridge layer between the first semiconductor layer (208) and the second semiconductor layer (206). Forming the non-planar channel region can include forming a nanosheet stack over a substrate (204), forming a trench (502) by removing a portion of the nanosheet stack, and forming a third semiconductor layer (602) in the trench (502). Outer surfaces of the first semiconductor layer (208), the second semiconductor layer (206), and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

公开(公告)号：GB2600667A

公开(公告)日：2022-05-04

申请号：GB202202974

申请日：2020-08-06

Applicant: IBM

Inventor： CHANRO PARK ,  NICHOLAS ANTHONY LANZILLO ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER ,  BALASUBRAMANIAN PRANATHARTHI HARAN

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure (100) includes an interlayer dielectric (ILD) (112) having a cavity (122) extending therethrough along a first direction. A first electrically conductive strip (110) is formed on a substrate (102) and within the cavity (122). The first electrically conductive strip (110) extends along the first direction and across an upper surface of the substrate (102). A second electrically conductive strip (118) is on an upper surface of the ILD (112) and extends along a second direction opposite the first direction. A fully aligned via (FAV) (124) extends between the first and second electrically conductive strips (110, 118) such that all sides of the FAV (124) are co-planar with opposing sides of the first electrically conductive strip (110) and opposing sides of the second electrically conductive strip (118) thereby providing a FAV (124) that is fully aligned with the first electrically conductive strip (110) and the second electrically conductive strip (118).

公开(公告)号：SG2013068614A

公开(公告)日：2014-09-26

申请号：SG2013068614

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC ,  IBM

Inventor： RUILONG XIE ,  CHANRO PARK ,  SHOM PONOTH

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

公开(公告)号：GB2604518A

公开(公告)日：2022-09-07

申请号：GB202207339

申请日：2020-10-12

Applicant: IBM

Inventor： CHANRO PARK ,  CHENG KANGGUO ,  RUILONG XIE ,  CHOONGHYUN LEE

IPC: H01L27/105

Abstract: A semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming by atomic layer deposition in the cell contact hole a second dielectric layer including a seam; forming a bottom electrode within the cavity and in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and in contact with the second dielectric layer and the seam.

公开(公告)号：GB2603283A

公开(公告)日：2022-08-03

申请号：GB202117763

申请日：2021-12-09

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method including: forming a source/drain on an exposed portion of a semiconductor layer 123,126 of a layered nanosheet; forming a sacrificial material on the source/drain; forming a dielectric layer 205 covering the sacrificial material; and replacing the sacrificial material with a contact liner 240. Also disclosed is a semiconductor device including: a first gate nanosheet stack and second gate nanosheet stack; a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack; a source/drain dielectric 205 located between the first source/drain and the second source/drain; and a contact liner 240 in contact with the first source/drain, the second source/drain and the source/drain dielectric 205. Further disclosed is the method of forming the semiconductor device using the above method.

公开(公告)号：GB2634478A

公开(公告)日：2025-04-09

申请号：GB202500991

申请日：2023-07-31

Applicant: IBM

Inventor： CHANRO PARK ,  JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG

IPC: H10B63/00 ,  H10N70/20

Abstract: A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.

公开(公告)号：GB2631071A

公开(公告)日：2024-12-18

申请号：GB202414743

申请日：2023-03-23

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

IPC: H01L29/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

公开(公告)号：GB2603283B

公开(公告)日：2023-01-18

申请号：GB202117763

申请日：2021-12-09

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment includes a method of forming a semiconductor device and the resulting device. The method may include forming a source/drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method may include forming a sacrificial material on the source/drain. The method may include forming a dielectric layer covering the sacrificial material. The method may include replacing the sacrificial material with a contact liner. The semiconductor device may include a first gate nanosheet stack and second gate nanosheet stack. The semiconductor device may include a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack. The semiconductor device may include a source/drain dielectric located between the first source/drain and the second source/drain. The semiconductor device may include a contact liner in contact with the first source/drain, the second source/drain and the source/drain dielectric.

公开(公告)号：GB2595125B

公开(公告)日：2022-11-09

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.