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公开(公告)号:JPH1145157A
公开(公告)日:1999-02-16
申请号:JP19872897
申请日:1997-07-24
Applicant: IBM
Inventor: SATO MASAHIKO , KAKIHARA TOSHIO , KANAMARU ATSUSHI , OSHIKAWA HIROSHI , ASANO HIDEO
Abstract: PROBLEM TO BE SOLVED: To permit high-reliability data transfer and a minimum throughput decrease by controlling data transfer to a 2nd data transfer speed slower than a 1st data transfer speed once an error detecting means detects a specific error. SOLUTION: A hard disk drive(HDD) is equipped with a hard disk controller 105A which controls operation for reading and writing data out of and to a magnetic disk 101 and an MPU 106 which controls the operation of the whole HDD. To transfer data from the HDD 100 to a host 200, the 1st data transfer speed is set first and the data are transferred from the HDD to the host 200 at the 1st data transfer speed. If a specific error is detected in the transferred data, the data transfer speed is changed to the 2nd transfer speed slower than the 1st transfer speed. Consequently, the state of the IDEI/FBus can be known by monitoring the status of the existent CRC error, so high-reliability data transfer for reading can be performed only by alterations of the drive side.
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公开(公告)号:JP2002182810A
公开(公告)日:2002-06-28
申请号:JP2000370626
申请日:2000-12-05
Applicant: IBM
Inventor: OSHIKAWA HIROSHI , SHIMIZU MASAHIRO , YAMADA MITSUHARU , OMORI TADASHI
Abstract: PROBLEM TO BE SOLVED: To improve the reliability of data transfer by increasing timing margin without lowering data transfer speed. SOLUTION: The slew rate controller of a driver independently controls the slew rate of a data signal and the slew rate of a control signal of a strobe signal, etc., and the slew rate of the data signal is made smaller than the slew rate of the strobe signal. Namely, a waveform inclination in the transition time of the strobe signal is made larger than that of the data signal in a signal waveform.
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公开(公告)号:JP2001222474A
公开(公告)日:2001-08-17
申请号:JP2000029103
申请日:2000-02-07
Applicant: IBM
Inventor: OSHIKAWA HIROSHI , SAKAI TATSUYA , ASANO HIDEO , SATO MASAHIKO
IPC: G06F3/00 , G06F13/00 , G06F13/38 , H03K19/0175 , H03K19/0185 , H04L1/00 , H04L25/02
Abstract: PROBLEM TO BE SOLVED: To realize a high signal integrity at all settable data transfer speeds. SOLUTION: A signal output device capable of setting up plural different data transfer speeds and outputting a signal to a signal receiver at a certain set data transfer speed via an ATA cable 2 is provided with a driver circuit 53 capable of setting up plural different through rates and outputting the signal to the ATA cable 2 at a through rate set in accordance with a through rate control signal SRC and a control means for setting up the through rate of the driver circuit 53 in accordance with the set data transfer speed.
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