公开(公告)号：EP2232548A4

公开(公告)日：2013-02-27

申请号：EP08866597

申请日：2008-12-22

Applicant: IBM

Inventor： BASKER VEERARAGHAVAN S ,  PARUCHURI VAMSI ,  COTTE JOHN M ,  FURUKAWA TOSHIHARU ,  TONTI WILLIAM ,  DELIGIANNI HARIKLIA

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L29/517 ,  H01L29/66545

公开(公告)号：WO2015032274A9

公开(公告)日：2016-03-24

申请号：PCT/CN2014084756

申请日：2014-08-20

Applicant: IBM ,  IBM CHINA CO LTD

Inventor： NACZAS SEBASTIAN ,  PARUCHURI VAMSI ,  REZNICEK ALEXANDER ,  SCHEPIS DOMINIC J

IPC: H01L29/78

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

Abstract translation: 可以通过形成在其上形成这种接触的无缺陷表面来实现对finFET源极/漏极的低电阻接触。 finFET的翅片可以暴露于外延生长条件以增加源极/漏极中的半导体材料的体积。 面对增长的前沿可以合并或形成未成熟的方面。 电介质材料可以填充源极漏极区域内的空隙。 与finFET栅极隔开的沟槽可以暴露在所述沟槽内的鳍片上的刻面外延生长的顶部，这些顶部由光滑电介质表面分开。 选择性地形成在暴露在沟槽内的顶部上的硅层可以转化为半导体金属层，将这种接触与源极漏极区域中的各个鳍连接。

公开(公告)号：WO2009019187A3

公开(公告)日：2009-04-02

申请号：PCT/EP2008060022

申请日：2008-07-30

Applicant: IBM ,  CARTIER EDUARD ALBERT ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI ,  LINDER BARRY PAUL ,  DORIS BRUCE

Inventor： CARTIER EDUARD ALBERT ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI ,  LINDER BARRY PAUL ,  DORIS BRUCE

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators (10, 11) and metal containing gates. The metal layers (70, 71) of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

Abstract translation: 公开了具有高k介质栅绝缘体（10,11）和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层（70,71）已经由单个公共金属层制造。 由于单个普通金属，器件制造简化，需要减少数量的掩模。 此外，作为使用单层金属作为两种类型的器件的栅极的进一步的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过选择普通金属材料和高k电介质的氧气曝光来调节器件阈值。 阈值是针对低功耗设备操作的。