公开(公告)号：JP2002231727A

公开(公告)日：2002-08-16

申请号：JP2002004201

申请日：2002-01-11

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUPUIS MARK D ,  GALLAGHER MATTHEW D ,  PETER J JEAYES ,  PHILIPS BRETT A

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiGe heterojunction bipolar transistor which reduces the SiGe base resistance. SOLUTION: An SiGe heterojunction bipolar transistor comprises a semiconductor substrate with a collector and a subcollector. The collector and the subcollector are formed between isolation regions existing within the substrate. Each isolation region comprises a recessed surface and a nonrecessed surface and these surfaces are formed by a lithography and an etching. An SiGe layer is formed on the substrate and the recessed and nonrecessed surfaces of each isolation region. The SiGe layer comprises a polycrystalline Si region and an SiGe base region. A patterned insulating layer is formed on the SiGe base region and moreover, an emitter is formed on the patterned insulating layer and comes into contact with the SiGe base region through an emitter window aperture.

公开(公告)号：WO2011163429A3

公开(公告)日：2012-02-23

申请号：PCT/US2011041546

申请日：2011-06-23

Applicant: IBM ,  GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L28/55 ,  H01L27/11507

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20,44a) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (44a) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20,44a）形成到顶板（32）和底板（28）。 至少到顶板（32）的接触（44a）和与CMOS结构的扩散的接触（20）通过公共电线电连接。

公开(公告)号：GB2494362B

公开(公告)日：2015-05-20

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：DE112011102131T5

公开(公告)日：2013-03-28

申请号：DE112011102131

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MURPHY WILLIAM J ,  PHILIPS BRETT A ,  MOON MATTHEW D ,  NAKOS JAMES S ,  PASTEL PAUL W

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

Abstract: Ferroelektrischer Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen. Das Herstellungsverfahren eines ferroelektrischen Kondensators beinhaltet das Ausbilden einer Barriereschicht auf einer Isolationsschicht (18) einer CMOS-Struktur (10). Das Verfahren beinhaltet weiterhin das Ausbilden einer oberen Platte (32) und einer untern Platte (28) über der Barriereschicht. Weiterhin beinhaltet das Verfahren das Ausbilden eines ferroelektrischen Materials (30) zwischen der oberen Platte (32) und der unteren Platte (28). Das Verfahren beinhaltet weiterhin die Ummantelung der Barriereschicht, der oberen Platte (32), der unteren Platte (28) und des ferroelektrischen Materials (30) mit einem Ummantelungsmaterial (36). Das Verfahren beinhaltet weiterhin das Ausbilden von Kontakten (20) mit der oberen Platte (32) und der unteren Platte (28) durch das Ummantelungsmaterial (36). Wenigstens der Kontakt (20) mit der oberen Platte (32) und ein Kontakt (20) mit einer Diffusion der CMOS-Struktur stehen durch eine gemeinsame Leitung in elektrischer Verbindung.

公开(公告)号：GB2494362A

公开(公告)日：2013-03-06

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (20) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.