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    METHOD AND DEVICE FOR DEPOSITING COBALT
    3.
    发明专利
    METHOD AND DEVICE FOR DEPOSITING COBALT 失效

    公开(公告)号：JPH11317380A

    公开(公告)日：1999-11-16

    申请号：JP4384099

    申请日：1999-02-22

    Applicant: IBM

    Inventor： MURPHY WILLIAM J ,  PRABHATTO TIWARI

    IPC: C23C14/14 ,  C23C14/16 ,  C23C14/34 ,  C23C14/58 ,  H01L21/285

    Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for forming cobalt on a silicon substrate which contains a specific oxide on its surface. SOLUTION: An improved sputtering apparatus 10 is used. The sputtering apparatus 10 is improved, in such a manner that it is provided with an electric circuit 18 to be connected to a ground. A wafer 17 disposed in the apparatus is electrically connected to a ground circuit 18. The ground circuit 18 preferably includes a resistor 19 inside for controlling the wafer potential and the current from the wafer to the ground. By supplying a current from the wafer to the ground, preferably a ground circuit including a resistor, the cleaning of the specific oxide on the surface of the silicon and deposition of cobalt on the silicon which has been cleaned can be performed at the same time, as it is. Immediately after that, the substrate having deposited cobalt on is surface is annealed, and flat and uniform cobalt silicide is formed over a specified region of the surface of a wafer.

    FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
    5.
    发明申请
    FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    电力电容器模块，制造方法和设计结构

    公开(公告)号：WO2011163429A3

    公开(公告)日：2012-02-23

    申请号：PCT/US2011041546

    申请日：2011-06-23

    Applicant: IBM ,  GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

    Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

    IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L28/55 ,  H01L27/11507

    Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20,44a) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (44a) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

    Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20,44a）形成到顶板（32）和底板（28）。 至少到顶板（32）的接触（44a）和与CMOS结构的扩散的接触（20）通过公共电线电连接。

    TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE
    7.
    发明申请
    TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
    基于铝的电阻互连结构的TUNGSTEN LINER

    公开(公告)号：WO2009117255A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2009036091

    申请日：2009-03-05

    Applicant: IBM ,  CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

    Inventor： CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

    IPC: H01L21/4763

    CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack (360L, Figure 5) comprising, from bottom to top, a low-oxygen-reactivity metal layer (10), a bottom transition metal layer (20), a bottom transition metal nitride layer (30), an aluminum-copper layer (40), an optional top transition metal layer (50), and a top transition metal nitride layer (60). The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen- reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

    Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 从底部到顶部包含低氧反应性金属层（10），底部过渡金属层（20），底部过渡金属氮化物层（30），铝合金（30）的金属层堆叠（360L，图5） （40），可选的顶部过渡金属层（50）和顶部过渡金属氮化物层（60）。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和介电材料层之间的化合物的形成，从而提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

    Planar cavity MEMS and related structures, methods of manufacture and design structures
    8.
    发明专利
    Planar cavity MEMS and related structures, methods of manufacture and design structures 未知

    公开(公告)号：GB2494360B

    公开(公告)日：2013-09-18

    申请号：GB201300091

    申请日：2011-06-08

    Applicant: IBM

    Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  MALING JEFFREY C

    IPC: B81C1/00

    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

    Ferroelektrische Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen
    10.
    发明专利
    Ferroelektrische Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen 未知

    公开(公告)号：DE112011102131T5

    公开(公告)日：2013-03-28

    申请号：DE112011102131

    申请日：2011-06-23

    Applicant: IBM

    Inventor： GAMBINO JEFFREY P ,  MURPHY WILLIAM J ,  PHILIPS BRETT A ,  MOON MATTHEW D ,  NAKOS JAMES S ,  PASTEL PAUL W

    IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

    Abstract: Ferroelektrischer Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen. Das Herstellungsverfahren eines ferroelektrischen Kondensators beinhaltet das Ausbilden einer Barriereschicht auf einer Isolationsschicht (18) einer CMOS-Struktur (10). Das Verfahren beinhaltet weiterhin das Ausbilden einer oberen Platte (32) und einer untern Platte (28) über der Barriereschicht. Weiterhin beinhaltet das Verfahren das Ausbilden eines ferroelektrischen Materials (30) zwischen der oberen Platte (32) und der unteren Platte (28). Das Verfahren beinhaltet weiterhin die Ummantelung der Barriereschicht, der oberen Platte (32), der unteren Platte (28) und des ferroelektrischen Materials (30) mit einem Ummantelungsmaterial (36). Das Verfahren beinhaltet weiterhin das Ausbilden von Kontakten (20) mit der oberen Platte (32) und der unteren Platte (28) durch das Ummantelungsmaterial (36). Wenigstens der Kontakt (20) mit der oberen Platte (32) und ein Kontakt (20) mit einer Diffusion der CMOS-Struktur stehen durch eine gemeinsame Leitung in elektrischer Verbindung.

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