公开(公告)号：EP1792343A4

公开(公告)日：2009-11-11

申请号：EP05754954

申请日：2005-05-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/20 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

公开(公告)号：WO2005122245A2

公开(公告)日：2005-12-22

申请号：PCT/US2005018521

申请日：2005-05-26

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层（100）的上方形成介电层（102,106），在电介质层的上方形成上导体层（104,108）。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层（200），并在蚀刻停止层上形成硬掩模（202）（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上图案化光致抗蚀剂（300），其允许通过光刻胶蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：WO2012047458A2

公开(公告)日：2012-04-12

申请号：PCT/US2011051348

申请日：2011-09-13

Applicant: IBM ,  DEMUYNCK DAVID A ,  HE ZHONG-XIANG ,  MIGA DANIEL R ,  MOON MATTHEW D ,  VANSLETTE DANIEL S ,  WHITE ERIC J

Inventor： DEMUYNCK DAVID A ,  HE ZHONG-XIANG ,  MIGA DANIEL R ,  MOON MATTHEW D ,  VANSLETTE DANIEL S ,  WHITE ERIC J

IPC: H01L21/28

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，并且更具体地涉及高性能电感器。 IC（10）包括设置在衬底（30）上的电介质层（25）内的至少一个沟槽（20）。 沟槽共形涂覆有衬里和籽晶层（35），并且包括内部的互连（40）。 该互连包括互连侧壁上的硬掩模（45）。

公开(公告)号：WO2011163429A3

公开(公告)日：2012-02-23

申请号：PCT/US2011041546

申请日：2011-06-23

Applicant: IBM ,  GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L28/55 ,  H01L27/11507

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20,44a) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (44a) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

Abstract translation: 铁电电容器模块，制造方法和设计结构。 制造铁电电容器的方法包括在CMOS结构（10）的绝缘体（18）层上形成阻挡层。 该方法还包括在阻挡层上形成顶板（32）和底板（28）。 该方法还包括在顶板（32）和底板（28）之间形成铁电材料（30）。 该方法还包括用封装材料（36）封装阻挡层，顶板（32），底板（28）和铁电材料（30）。 该方法还包括通过封装材料（36）将接触件（20,44a）形成到顶板（32）和底板（28）。 至少到顶板（32）的接触（44a）和与CMOS结构的扩散的接触（20）通过公共电线电连接。

公开(公告)号：GB2494362A

公开(公告)日：2013-03-06

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (20) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：GB2494362B

公开(公告)日：2015-05-20

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：GB2498154B

公开(公告)日：2014-05-07

申请号：GB201307079

申请日：2011-09-13

Applicant: IBM

Inventor： DEMUYNCK DAVID ,  HE ZHONG-XIANG ,  MIGA DANIEL ,  MOON MATTHEW D ,  VANSLETTE DANIEL ,  WHITE ERIC J

IPC: H01L21/768 ,  H01L23/522

公开(公告)号：DE112011103400T5

公开(公告)日：2013-08-22

申请号：DE112011103400

申请日：2011-09-13

Applicant: IBM

Inventor： MIGA DANIEL R ,  MOON MATTHEW D ,  HE ZHONG-XIANG ,  VANSLETTE DANIEL S ,  WHITE ERIC J ,  DEMUYNCK DAVID A

IPC: H01L21/28

Abstract: Die Offenbarung betrifft allgemein integrierte Schaltungen (ICs), IC-Verbindungen und Verfahren zur Herstellung derselben und insbesondere Hochleistungsinduktoren. Die IC (10) weist mindestens einen Graben (20) innerhalb einer Dielektrikumsschicht (25) auf, die auf einem Substrat (30) angeordnet ist. Der Graben wird formangepasst mit einer Auskleidungs- und Keimschicht (35) beschichtet und weist eine Verbindung (40) darin auf. Die Verbindung weist eine Hartmaske (45) auf den Seitenwänden der Verbindung auf.

公开(公告)号：GB2498154A

公开(公告)日：2013-07-03

申请号：GB201307079

申请日：2011-09-13

Applicant: IBM

Inventor： DEMUYNCK DAVID ,  HE ZHONG-XIANG ,  MIGA DANIEL ,  MOON MATTHEW D ,  VANSLETTE DANIEL ,  WHITE ERIC J

IPC: H01L21/768 ,  H01L23/522

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

公开(公告)号：DE112011102131T5

公开(公告)日：2013-03-28

申请号：DE112011102131

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MURPHY WILLIAM J ,  PHILIPS BRETT A ,  MOON MATTHEW D ,  NAKOS JAMES S ,  PASTEL PAUL W

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

Abstract: Ferroelektrischer Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen. Das Herstellungsverfahren eines ferroelektrischen Kondensators beinhaltet das Ausbilden einer Barriereschicht auf einer Isolationsschicht (18) einer CMOS-Struktur (10). Das Verfahren beinhaltet weiterhin das Ausbilden einer oberen Platte (32) und einer untern Platte (28) über der Barriereschicht. Weiterhin beinhaltet das Verfahren das Ausbilden eines ferroelektrischen Materials (30) zwischen der oberen Platte (32) und der unteren Platte (28). Das Verfahren beinhaltet weiterhin die Ummantelung der Barriereschicht, der oberen Platte (32), der unteren Platte (28) und des ferroelektrischen Materials (30) mit einem Ummantelungsmaterial (36). Das Verfahren beinhaltet weiterhin das Ausbilden von Kontakten (20) mit der oberen Platte (32) und der unteren Platte (28) durch das Ummantelungsmaterial (36). Wenigstens der Kontakt (20) mit der oberen Platte (32) und ein Kontakt (20) mit einer Diffusion der CMOS-Struktur stehen durch eine gemeinsame Leitung in elektrischer Verbindung.