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    A METHOD FOR FORMING SELF-ALIGNED FEATURES
    3.
    发明专利
    A METHOD FOR FORMING SELF-ALIGNED FEATURES 未知

    公开(公告)号：MY118631A

    公开(公告)日：2004-12-31

    申请号：MYPI9904305

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/4763 ,  H01L21/027 ,  H01L21/768

    Abstract: THE PRESENT INVENTION PROVIDES FOR AN IMPROVED METHOD OF CREATING VIAS (730, 735) AND TRENCHES (737-739) DURING MICROCHIP FABRICATION. ACCORDING TO THE INVENTION, THE VIAS AND TRENCHES ARE SELF-ALIGNED DURING THE PHOTOLITHOGRAPHY PROCESS BY USING TWO LAYERS OF SPECIALLY SELECTED RESISTS (205, 210, 1804, 1806) AND EXPOSING THE RESISTS SUCH THAT THE LOWER RESIST IS EXPOSED ONLY WHERE AN OPENING HAS BEEN FORMED IN THE UPPER RESIST LAYER. THIS SELF-ALIGNING ENABLES THE VIAS TO BE PRINTED AS ELONGATED SHAPES, WHICH ALLOWS FOR THE USE OF PARTICULARLY EFFECTIVE IMAGE ENHANCEMENT TECHNIQUES. THE INVENTION FURTHER PROVIDES A SIMPLIFIED PROCEDURE FOR CREATING VIAS AND TRENCHES, IN THAT ONLY ONE ETCH STEP IS REQUIRED TO SIMULTANEOUSLY CREATE BOTHVIAS AND TRENCHES. AN ALTERNATIVE EMBODIMENT OF THE INVENTION ALLOWS LOOPED OR LINKED IMAGES, SUCH AS THOSE PRINTED USING IMAGE ENHANCEMENT TECHNIQUES, TO BE TRIMMED TO FORM ISOLATED FEATURES.

    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY
    4.
    发明专利
    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY 未知

    公开(公告)号：MY117065A

    公开(公告)日：2004-04-30

    申请号：MYPI9904306

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/22 ,  H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78

    Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FORMING SELF-ALIGNED SPACERS (502) ON THE HORIZONTAL SURFACES WHILE REMOVING SPACER MATERIAL FROM THE VERTICAL SURFACES. THE PREFERRED METHOD USES A RESIST(302) THAT CAN BE MADE INSOLUBLE TO DEVELOPER BY THE USE OF AN IMPLANT. BY CONFORMALLY DEPOSITING THE RESIST OVER A SUBSTRATE (202) HAVING BOTH VERTICAL AND HORIZONTAL SURFACES, IMPLANTING THE RESIST, AND DEVELOPING THE RESIST, THE RESIST IS REMOVED FROM THE VERTICAL SURFACES WHILE REMAINING ON THE HORIZONTAL SURFACES. THUS, A SELF-ALIGNED SPACER IS FORMED ON THE HORIZONTAL SURFACES WHILE THE SPACER MATERIAL IS REMOVED FROM THE VERTICAL SURFACES. THIS HORIZONTAL-SURFACE SPACER CAN THEN BE USED IN FURTHER FABRICATION. THE PREFERRED METHOD CAN BEUSED IN MANY DIFFERENT PROCESSES WHERE THERE IS EXISTS A NEED TO DIFFERENTIALLY PROCESS THE VERTICAL AND HORIZONTAL SURFACES OF A SUBSTRATE.FIG. 1

    5.
    发明专利
    未知

    公开(公告)号：DE60233241D1

    公开(公告)日：2009-09-17

    申请号：DE60233241

    申请日：2002-08-29

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

    IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING
    6.
    发明专利
    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING 未知

    公开(公告)号：MY117201A

    公开(公告)日：2004-05-31

    申请号：MYPI9904530

    申请日：1999-10-20

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: G03C5/00 ,  H01L21/28 ,  H01L21/027 ,  H01L21/302 ,  H01L21/32 ,  H01L21/60 ,  H01L21/768

    Abstract: A METHOD FOR FORMING CONTACTS ON AN INTEGRATED CIRCUIT THAT ARE SELF-ALIGNED WITH THE WIRING PATTERNS OF THE INTEGRATED CIRCUIT. IN THE METHOD A THICKER LOWER LAYER (12) OF A FIRST MATERIAL AND A THINNER UPPER LAYER (14) OF A SECOND MATERIAL ARE FORMED ON A SUBSTRATE (10). THE FEATURES OF THE METAL WIRING IS PATTERNED FIRST ON THE UPPER LAYER. THE WIRING PATTERN TRENCHES (20) ARE ETCHED THROUGH THE THINNER SURFACE LAYER, AND PARTIALLY THROUGH THE SECOND, THICKER LAYER. AFTER THE WIRING PATTERN IS ETCHED, THE CONTACTS FOR THE WIRING LAYER ARE PRINTED AS LINE/SPACE PATTERNS WHICH INTERSECT THE WIRING PATTERN. THE CONTACT PATTERN IS ETCHED INTO THE LOWER, THICKER LAYER WITH AN ETCH PROCESS THAT IS SELECTIVE TO THE UPPER THINNER LAYER. THE CONTACT IS ONLY FOFFI1ED AT THE INTERSECTION POINT OF THE WIRING IMAGE WITH THE CONTACT IMAGE, THEREFORE THE CONTACT IS SELF-ALIGNED TO THE METAL (24).

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