公开(公告)号：EP1430536A4

公开(公告)日：2006-04-26

申请号：EP02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

公开(公告)号：WO03019671A3

公开(公告)日：2003-04-10

申请号：PCT/US0228265

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.

Abstract translation: 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻形成的半导体柱（2910）的相对侧的潜在独立的栅极结构（3230）。 栅极结构由绝缘材料（2620）包围，其被选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，将一个触点（3820）制成在支柱的下端。 柱的上端由盖​​（2730）和选择性可蚀刻材料的侧壁覆盖，使得栅极和源极连接开口（3720,3620）也可以通过具有良好配准公差的选择性蚀刻制成。

公开(公告)号：DE60233241D1

公开(公告)日：2009-09-17

申请号：DE60233241

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

公开(公告)号：CA2006229A1

公开(公告)日：1990-09-14

申请号：CA2006229

申请日：1989-12-20

Applicant: IBM

Inventor： BECKHAM KEITH F ,  CHALLENER DAVID C ,  GUPTA ARUNAVA ,  HARVILCHUCK JOSEPH M ,  LEAS JAMES M ,  LLOYD JAMES R ,  LONG DAVID C ,  QUINONES HORATIO ,  SESHAN KRISHNA ,  SHATZKES MORRIS

IPC: B23K26/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H05K3/22 ,  G01R31/26

Abstract: METHOD AND APPARATUS FOR CAUSING AN OPEN CIRCUIT IN A CONDUCTIVE LINE A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor. . FI9-88-027