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公开(公告)号：DE2555963A1
公开(公告)日：1977-06-16
申请号：DE2555963
申请日：1975-12-12
Applicant: IBM DEUTSCHLAND
Inventor： BLUM ARNOLD DIPL ING , IRRO FRITZ DIPL ING , HEYDEN HORST VON DER , RICHTER STEPHAN , SCHULZE-SCHOELLING HERMANN , SCHAAL HELMUT
IPC: G06F12/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/06 , G06F15/16 , G06F15/177 , G06F9/18
Abstract: 1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain external and/or internal non-program conditions are satisfied. The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set.
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公开(公告)号：BR8902352A
公开(公告)日：1990-01-09
申请号：BR8902352
申请日：1989-05-19
Applicant: IBM
Inventor： BOCK DIETRICH W , GRASSMANN KURT , RUDOLPH PETER , SCHULZE-SCHOELLING HERMANN
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公开(公告)号：CA1113575A
公开(公告)日：1981-12-01
申请号：CA340653
申请日：1979-11-26
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH R , SCHULZE-SCHOELLING HERMANN
Abstract: CLOCK CHECK CIRCUITS USING DELAYED SIGNALS In a data processing or transmission system which includes at least two synchronized clocks, for example - T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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Patent Agency Ranking
公开(公告)号：CA1311308C
公开(公告)日：1992-12-08
申请号：CA592547
申请日：1989-03-02
Applicant: IBM
Inventor： BOCK DIETRICH W , SCHULZE-SCHOELLING HERMANN , KUMPF WOLFGANG , RUDOLPH PETER
IPC: G06F15/16 , G06F9/38 , G06F9/46 , G06F9/52 , G06F15/177
Abstract: Processor-Processor Synchronization For synchronizing the operations of a processor with a co-processor, a single instruction is used which combines determining the co-processor's busy status with determining the presence of an exceptional status in the co-processor. Both tests are executed during a time period not longer than the time period required for executing a single test.
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公开(公告)号：CA1316608C
公开(公告)日：1993-04-20
申请号：CA594646
申请日：1989-03-23
Applicant: IBM
Inventor： BOCK DIETRICH W , GRASSMANN KURT , RUDOLPH PETER , SCHULZE-SCHOELLING HERMANN
Abstract: Arrangement for Error Recovery in a Self-Guarding Data Processing System In self-guarding data processing systems most of the error handling activities have to be implemented without any program support from a dedicated subsystem which is secured against the error problems which it has to handle. The self-guarding data processing system must be reset and restarted to handle the error procedures by itself. This means that the error status manifested in many check latches has to survive the reset and restart activities and that it has to be accessible by instructions within the processor in error. Check indicator latches are provided which are set by the error signals and which are read by the error handling program routines for further evaluation. They can only be reset by the error handling program routines.
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公开(公告)号：IT1165393B
公开(公告)日：1987-04-22
申请号：IT2774079
申请日：1979-11-30
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOELLING HERMANN , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：IT7927740D0
公开(公告)日：1979-11-30
申请号：IT2774079
申请日：1979-11-30
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOELLING HERMANN , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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