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公开(公告)号：AU5343379A
公开(公告)日：1980-06-19
申请号：AU5343379
申请日：1979-12-04
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHOELLING HERMANN SCHULZE , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：CH632349A5
公开(公告)日：1982-09-30
申请号：CH1001078
申请日：1978-09-26
Applicant: IBM
Inventor： BAZLEN DIETER , BERGER ROLF , BLUM ARNOLD , BOCK DIETRICH W , CHILINSKI HERBERT , GENG HELLMUTH ROLAND , HAJDU JOHANN , IRRO FRITZ , NEUBER SIEGFRIED , WILLE UDO
IPC: G06F9/22
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公开(公告)号：AU528615B2
公开(公告)日：1983-05-05
申请号：AU5343379
申请日：1979-12-04
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHOELLING HERMANN SCHULZE , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：DE2756764A1
公开(公告)日：1979-06-21
申请号：DE2756764
申请日：1977-12-20
Applicant: IBM DEUTSCHLAND
Inventor： BLUM ARNOLD DIPL ING , BAZLEN DIETER DR ING , BERGER ROLF DIPL ING , BOCK DIETRICH DIPL ING , CHILINSKI HERBERT DIPL ING , GENG HELLMUTH ROLAND , GETZLAFF KLAUS ING GRAD , HAJDU JOHANN , RICHTER STEPHAN
Abstract: The synchronising arrangement is for a processor and memory in an electronic data processing installation. There is a delay from the memory when data is demanded from it by the processor. A section of the arrangement has an output to the operations register of the processor for the provision of a code combination corresponding to a certain micro-instruction lasting for the duration of the memory delay. The operations decoder provides a corresponding output signal which stops the demand cycle counter. The operations register loads the next operation code existing at its input when it receives the next pulse of the system.
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公开(公告)号：DE2963788D1
公开(公告)日：1982-11-11
申请号：DE2963788
申请日：1979-10-23
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOLLING HERMANN , SPATH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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Patent Agency Ranking
公开(公告)号：DE2747304A1
公开(公告)日：1979-04-26
申请号：DE2747304
申请日：1977-10-21
Applicant: IBM DEUTSCHLAND
Inventor： BAZLEN DIETER DIPL ING DR , BERGER ROLF DIPL ING , BLUM ARNOLD DIPL ING , BOCK DIETRICH DIPL ING , CHILINSKI HERBERT DIPL ING , GENG HELLMUTH ROLAND , HAJDU JOHANN , IRRO FRITZ DIPL ING , NEUBER SIEGFRIED , WILLE UDO
Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
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公开(公告)号：IT1165393B
公开(公告)日：1987-04-22
申请号：IT2774079
申请日：1979-11-30
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOELLING HERMANN , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：IT7927740D0
公开(公告)日：1979-11-30
申请号：IT2774079
申请日：1979-11-30
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOELLING HERMANN , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：DE2758146A1
公开(公告)日：1979-06-28
申请号：DE2758146
申请日：1977-12-27
Applicant: IBM DEUTSCHLAND
Inventor： BLUM ARNOLD DIPL ING , CHILINSKI HERBERT DIPL ING , GENG HELLMUTH ROLAND , GETZLAFF KLAUS ING GRAD , HAJDU JOHANN , NEUBER SIEGFRIED , RICHTER STEPHAN , RUST BERND , WILLE UDO ING GRAD
Abstract: A control switching network is used in the programming circuit of a digital calculator. The processing unit is connected to a process timing and control unit. This unit is connected to a data store via a set of the intermediate connections. A system is used to keep the store in synchronism with the processing unit. An identification network is used, which produces a signal controlling the action of the store. Store activity monitoring signals are used, and instructions are given to the store in a series of given cycles.
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公开(公告)号：DE2140858A1
公开(公告)日：1973-03-08
申请号：DE2140858
申请日：1971-08-14
Applicant: IBM DEUTSCHLAND
Inventor： CHILINSKI HERBERT , GENG HELLMUTH ROLAND , HAJDU JOHANN
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