公开(公告)号：FR2406851B1

公开(公告)日：1986-04-11

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：BR8902352A

公开(公告)日：1990-01-09

申请号：BR8902352

申请日：1989-05-19

Applicant: IBM

Inventor： BOCK DIETRICH W ,  GRASSMANN KURT ,  RUDOLPH PETER ,  SCHULZE-SCHOELLING HERMANN

IPC: G06F11/00 ,  G06F11/07

公开(公告)号：CA1103366A

公开(公告)日：1981-06-16

申请号：CA312702

申请日：1978-10-04

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT

IPC: G06F9/22 ,  G06F9/00

Abstract: ARRANGEMENT FOR MICRO INSTRUCTION CONTROL In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：CA1316608C

公开(公告)日：1993-04-20

申请号：CA594646

申请日：1989-03-23

Applicant: IBM

Inventor： BOCK DIETRICH W ,  GRASSMANN KURT ,  RUDOLPH PETER ,  SCHULZE-SCHOELLING HERMANN

IPC: G06F11/00 ,  G06F11/07

Abstract: Arrangement for Error Recovery in a Self-Guarding Data Processing System In self-guarding data processing systems most of the error handling activities have to be implemented without any program support from a dedicated subsystem which is secured against the error problems which it has to handle. The self-guarding data processing system must be reset and restarted to handle the error procedures by itself. This means that the error status manifested in many check latches has to survive the reset and restart activities and that it has to be accessible by instructions within the processor in error. Check indicator latches are provided which are set by the error signals and which are read by the error handling program routines for further evaluation. They can only be reset by the error handling program routines.

公开(公告)号：FR2406851A1

公开(公告)日：1979-05-18

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：CA1311308C

公开(公告)日：1992-12-08

申请号：CA592547

申请日：1989-03-02

Applicant: IBM

Inventor： BOCK DIETRICH W ,  SCHULZE-SCHOELLING HERMANN ,  KUMPF WOLFGANG ,  RUDOLPH PETER

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177

Abstract: Processor-Processor Synchronization For synchronizing the operations of a processor with a co-processor, a single instruction is used which combines determining the co-processor's busy status with determining the presence of an exceptional status in the co-processor. Both tests are executed during a time period not longer than the time period required for executing a single test.

公开(公告)号：CH632349A5

公开(公告)日：1982-09-30

申请号：CH1001078

申请日：1978-09-26

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

公开(公告)号：AU4085678A

公开(公告)日：1980-04-24

申请号：AU4085678

申请日：1978-10-19

Applicant: IBM

Inventor： BAZLEN DIETER ,  NEUBER SIEGFRIED ,  WILLE UDO ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.