公开(公告)号：DE3161126D1

公开(公告)日：1983-11-10

申请号：DE3161126

申请日：1981-07-14

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BLUM ARNOLD

IPC: G06F12/16 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26 ,  G11C19/00

公开(公告)号：DE3160750D1

公开(公告)日：1983-09-15

申请号：DE3160750

申请日：1981-07-14

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BLUM ARNOLD

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/26 ,  G11C19/00

Abstract: LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by logically removing the master latches from the slave latches and by providing the slave latches with multiple shift inputs, e.g., two shift inputs (FIG. 2). The LSSD shifting philosophy remains unchanged to the extent that at the time of shifting, the virtual (not available slave latch) becomes real (physical) by assigning the only physical slave latch to the respective master latch. The present disclosure provides for multiple master latches to be dynamically assigned to one slave latch during shifting. This is in contrast to the known SRL chain approach requiring one slave latch for each master latch. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example (1) U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System" filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger, of common assignee herewith, or; (2) "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, pages 462-468, June 20, 21 and 22, 1977, New Orleans, Louisiana, IEEE Catalog Number 77, CH1216-1C.

公开(公告)号：DE3373729D1

公开(公告)日：1987-10-22

申请号：DE3373729

申请日：1983-12-08

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BLUM ARNOLD

IPC: G06F11/22 ,  G01R31/3185 ,  G11C19/00 ,  H03M9/00 ,  G06F11/26

Abstract: 1. Error testing and diagnostic device for an electronic data processing system having at least one processor, one main storage and one maintenance and service processor or tester interconnected by a fast system bus, wherein a serial test bus (13, 14) is provided supplying diagnostic information read from and/or written into the tester to storage elements combined in the form of shift chains, said storage elements being associated with logic subsystems for transferring test data into said subsystems and/or for reading result data, obtained by processing test data, into the tester for evaluation, characterized in that the storage elements (master/slave flip-flops 23, 24), interconnecting the logic subsystems (20; Figs. 2, 5 and 7) contained in a processor (9) during normal operation, are linked in the error test and diagnostic mode in the form of a garland-shaped shift register chain, whose beginning and end are connected by a controllable switch (44), wherein the storage elements, forming the stages (11, 12, ..., 1m) of the interface register, connected between the system bus (8) and the processor logic made up of the logic subsystems (20) and which serves both as a data receiving and transmitting register, are included in the shift register chain, so that test data from the maintenance and service processor (6) are transmitted in parallel on the system bus (8) to the interface register stages where they are entered in steps, through the garland-shaped shift register chain, into the logic subsystems, and that upon completion of testing, the result data of said logic subsystems are entered into the shift register chain from where they are transferred in steps to the interface register and from there in parallel on the system bus (8) to the maintenance and service processor (6) for error analysis and diagnosis.

公开(公告)号：DE3173631D1

公开(公告)日：1986-03-13

申请号：DE3173631

申请日：1981-09-10

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BLUM ARNOLD ,  SCHETTLER HELMUT

IPC: H03K19/00 ,  G01R31/316 ,  G01R31/317 ,  G01R31/319 ,  H03K19/0175 ,  G01R31/28

Abstract: An integrated circuit chip includes a tristate driver which assumes an active logical state in response to a data signal at its data input and assumes a high impedance state in response to a control signal at its control input. The integrated circuit chip also includes a control signal generating network which is connected to the tristate driver's control input for producing the control signal. The control signal generating network may be tested by connecting the control signal generating network to the data input and overriding the control input to prevent the tristate driver from assuming the high impedance state. Thus, for testing purposes, the proper response of the control signal generating circuit may be ascertained by monitoring the active state of the tristate driver.

公开(公告)号：AU5343379A

公开(公告)日：1980-06-19

申请号：AU5343379

申请日：1979-12-04

Applicant: IBM

Inventor： BLUM ARNOLD ,  GENG HELLMUTH ROLAND ,  SCHOELLING HERMANN SCHULZE ,  SPAETH BERND

IPC: G01R31/28 ,  G01R31/3183 ,  G04D7/00 ,  G06F1/04 ,  H03K5/26 ,  H04M3/22 ,  H04M3/24 ,  H03K5/18

Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

公开(公告)号：CA1139000A

公开(公告)日：1983-01-04

申请号：CA341347

申请日：1979-12-06

Applicant: IBM

Inventor： BLUM ARNOLD

IPC: G06F1/04 ,  G06F1/10

Abstract: DECENTRALIZED GENERATION OF SYNCHRONIZED CLOCK CONTROL SIGNALS In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuit means is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.

公开(公告)号：CH632349A5

公开(公告)日：1982-09-30

申请号：CH1001078

申请日：1978-09-26

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

公开(公告)号：AU4085678A

公开(公告)日：1980-04-24

申请号：AU4085678

申请日：1978-10-19

Applicant: IBM

Inventor： BAZLEN DIETER ,  NEUBER SIEGFRIED ,  WILLE UDO ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：IT1165393B

公开(公告)日：1987-04-22

申请号：IT2774079

申请日：1979-11-30

Applicant: IBM

Inventor： BLUM ARNOLD ,  GENG HELLMUTH ROLAND ,  SCHULZE-SCHOELLING HERMANN ,  SPAETH BERND

IPC: G01R31/3183 ,  G01R31/28 ,  G04D7/00 ,  G06F1/04 ,  H03K5/26 ,  H04M3/22 ,  H04M3/24 ,  H03K

Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.

公开(公告)号：IT1164524B

公开(公告)日：1987-04-15

申请号：IT2774179

申请日：1979-11-30

Applicant: IBM

Inventor： BLUM ARNOLD

IPC: G06F1/04 ,  G06F1/10 ,  G06F

Abstract: In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.