公开(公告)号：GB2462897A

公开(公告)日：2010-03-03

申请号：GB0909104

申请日：2009-05-28

Applicant: IBM

Inventor： WALTER JOERG ,  FELTEN LOTHAR ,  URBAN VOLKER ,  SMITH CHRISTOPHER

IPC: G06F11/26 ,  G01R31/317

Abstract: A method of debugging a hardware data processing device 10 having at least one state holding element and at least one logic unit with at least one combinatorial logic element, comprises extracting S10 a state of the device preferably by connecting the state holding elements of the device together to form at least one scan chain, the values of which are read out in a chip dump data file. The extracted state is transformed S20 into facilities and/or signal names used by a simulation model. Bits of the chip dump data file may be clustered in values corresponding with elements of the simulation model. The mapped facilities and/or signal names are loaded S30 into a simulator including the simulation model preferably by mapping them into a model initialisation file. The simulation model is run, preferably to evaluate S50 at least one logic unit without updating the state holding elements to generate an all event trace 30 which is just one cycle long and shows a transient value reconstruction. Alternatively, running the simulator model may comprise applying a clock signal and inputting external stimuli to generate an all event trace corresponding with the number of simulation cycles.

公开(公告)号：GB2455010B

公开(公告)日：2012-02-01

申请号：GB0822774

申请日：2008-12-15

Applicant: IBM

Inventor： KLEIN MATTHIAS ,  KOENIG ANDREAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER ,  WALZ MANFRED

IPC: G06F11/07