公开(公告)号：JPH1041458A

公开(公告)日：1998-02-13

申请号：JP5901397

申请日：1997-03-13

Applicant: IBM

Inventor： STEPHEN H BALDEMAN ,  JAMES M NEBER

IPC: H01L25/00 ,  H01L23/60 ,  H01L25/04 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To provide an ESD(electrostatic discharge) protection circuit and other buffer circuits such as decoupling capacitors, drivers and receivers, without occupying large areas on a core integrated circuit chip. SOLUTION: A package is composed of a complementary metal oxide semiconductor(CMOS) core integrated circuit ship 20, a support ship 22 and a lead 34 for external connection. The support ship 22 is provided with an ESD protection circuit and lead buffer circuits such as a decoupling capacitor, a driver and a receiver, for electrical connection with the core integrated circuit chip 20 and the leas 34. The yield and performance of a core integrated ship are improved by shifting the lead buffer circuits from the core ship and providing them on other support chips.

公开(公告)号：JP2001308280A

公开(公告)日：2001-11-02

申请号：JP2001070049

申请日：2001-03-13

Applicant: IBM

Inventor： STEPHEN H BALDEMAN ,  STAMPER ANTHONY K

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a precision circuit element and a method of forming it. SOLUTION: The circuit element is formed as one part of an integrated circuit assembly. The process of the circuit element provides a nominal value of the circuit element that is near to a desired value. An additional trim circuit element is coupled through a link to the nominal circuit element. The Link is a fusible link or an anti fuse. By fusing and cutting the fusible link selectively or by adding or reducing the trim circuit element by fusing the anti fuse, the nominal value of the circuit element is individuated. In a typical example, a capacitor is used.

公开(公告)号：JP2004221569A

公开(公告)日：2004-08-05

申请号：JP2003431428

申请日：2003-12-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PEQUIGNOT JAMES P ,  SLOAN JEFFREY H ,  STOUT DOUGLAS W ,  STEPHEN H BALDEMAN

IPC: H01L21/761 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/0255 ,  H01L27/0814 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrostatic discharge protective circuit in which triple well semiconductor device is used alone or in series construction. SOLUTION: The semiconductor device is preferably a diode junction construction. When the semiconductor device is used in a series construction, bias application can be controlled by using a control circuit. Regions 3 and 3A are n-doped, elongate up to a n-doped region 8 downwards, and forms a ring so as to separate a p-doped region 6 from a substrate region 10.The regions 3 and 3A can provide insulators of other size to separate the region 6. Moreover, the region 3 and 3A can be formed by using single implantation, or, by using a plurality of implantation of different energy or a quantity of dose. The region 6 is p-doped so as to make a separation from the substrate 10 possible. In this embodiment, a metallic junction of a p-n diode is formed on an area where the p-region 6 is adjacent to the region 3, the region 3A, and the region 8. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JPH11330384A

公开(公告)日：1999-11-30

申请号：JP20197998

申请日：1998-07-16

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  LEIDY ROBERT K ,  STEPHEN H BALDEMAN

IPC: G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/336 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enhance a CMOS device in latch up resistance, by a method wherein a side wall spacer/trough region is demarcated and formed by the use of hybrid photoresist which shows a positive-type, a negative type and an intermediate-type reaction to exposure light. SOLUTION: A gate oxide layer 2404 and a gate material layer 2406 are successively deposited on a wafer 2500, and side wall spacer troughs 2801 and 2802 are provided to the gate oxide layer 2404 and the gate material layer 2406 by the use of hybrid photoresist which shows a positive-type, a negative- type, and an intermediate-type reaction to exposure light. Three regions, a gate region 2804, a high source region 2806, and a high drain region 2808 are provided to the side wall spacer troughs 2801 and 2802, and a residual negative- type pattern 2526 and a residual hard mask layer 2408 are formed. By this setup, a CMOS device can be improved in latch-up resistance.