公开(公告)号：EP1839338A4

公开(公告)日：2011-11-09

申请号：EP05854112

申请日：2005-12-14

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

公开(公告)号：EP1817801A4

公开(公告)日：2010-07-28

申请号：EP05851917

申请日：2005-11-18

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  STAMPER ANTHONY K

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

公开(公告)号：JPH1174197A

公开(公告)日：1999-03-16

申请号：JP19292198

申请日：1998-07-08

Applicant: IBM

Inventor： JAMES A BRUCE ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  MLYNKO WALTER E ,  EDWARD W SENGL

IPC: G03F7/004 ,  G03F1/00 ,  G03F7/095 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To enable regions to be demarcated through a single masking step by a method, wherein a hybrid resist is irradiated with an actinic radiation energy to expose a first region on a mask, and a second region is exposed on the mask by uniform exposure. SOLUTION: An oxide layer and a nitride layer are formed on a wafer, and a hybrid resist layer is attached, exposed to light through a mask, and developed to form a space (302 to 308). The nitride layer is etched through the space (310), uniform exposure and development are carried out (312), and silicon is etched to the hybrid resist and the nitride layer to form an STI region (314). Then, the exposed nitride and the oxide are removed, a silicon dioxide layer is attached to an unblocked silicon, the nitride is etched (316 to 322), a nitride spacer is formed in an edge STI region, silicon dioxide is attached, a wafer is planarized and the residual nitride and the oxide are removed (324 to 330).

公开(公告)号：WO2006071540A3

公开(公告)日：2007-04-12

申请号：PCT/US2005045328

申请日：2005-12-14

Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：JPH1174196A

公开(公告)日：1999-03-16

申请号：JP19275998

申请日：1998-07-08

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  KAKU K HYUIN ,  LEIDY ROBERT K ,  PAUL W PASTELL

IPC: H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To enable junctions of a gate/source and a gate/drain to be enhanced in control in doping by a method, wherein a side wall spacer trough is demarcated by the use of a hybrid resist. SOLUTION: A wafer is prepared, and a hybrid resist layer is attached to the wafer, exposed to light through a mask, and developed (302 to 308) for the formation of a sidewall spacer. A hard mask is etched through a spacer (301), a uniform exposure process and a development process are carried out (312), a gate matter is etched through the residual hard mask (314), and a sidewall spacer trough is formed. Then, the exposed hard mask and a negative-type hybrid resist are removed (316 and 313), and a gate edge implant is formed (320). Then, a sidewall oxide and a nitride stopper are attached (322), an excess sidewall spacer matter and an excess gate matter are removed (326 and 328), and are injected (330) to a source and a drain region.

公开(公告)号：JPH08293554A

公开(公告)日：1996-11-05

申请号：JP9653496

申请日：1996-04-18

Applicant: IBM

Inventor： LEIDY ROBERT K ,  MILLER JEFFREY S ,  PATRICK JON A ,  PREVITI-KELLY ROSEMARY ANN

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To reduce a short circuit by forming a first via where a part of a substrate is exposed from the upper face of a polymer film through the film and a first insulating layer, a removing only a second insulating layer covering a metal interconnection stud end and forming a second via from the second insulating layer to the stud end. SOLUTION: The first via 60 which vertically extends from the upper surface 45 of the polymer film through the polymer film 40 and the first insulating layer 30 and exposes a part of the semiconductor substrate 20 is formed. Conductive metal is deposited to the first via 60 and it is planarized A metal interconnection stud 65 having the end making a plane with the upper surface 45 of the polymer film is formed. Then, the part of the second insulating layer 50 which directly covers the end 70 of the stud 65 is removed and the second via 80 extending to the stud end 70 through the second insulating layer 50 is formed. Thus, the short circuit of a metallization layer in the semiconductor device can be reduced.

公开(公告)号：JP2006324675A

公开(公告)日：2006-11-30

申请号：JP2006139399

申请日：2006-05-18

Applicant: IBM

Inventor： HOAGUE TIMOTHY J ,  LEIDY ROBERT K

IPC: H01L27/14 ,  G02B3/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for increasing a sensitivity of a pixel sensor. SOLUTION: A gap space is removed, which is formed between microlens structures of mutually adjacent pixel sensor arrays. Advantageously, by an exposure and flow conditions, the adjacent microlens structures are brought into contact with each other in a lateral sectional face (connected by web), thereby forming a round lens in all directions. Specifically, by the exposure and flow conditions, each lens of contacting microlens structure is formed in such a manner as matching with each other in a lateral cross section and 45° cross section to have a uniform curvature radius. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JPH1197449A

公开(公告)日：1999-04-09

申请号：JP12084598

申请日：1998-04-30

Applicant: IBM

Inventor： BROWN JEFFREY S ,  HOLMES STEVEN J ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

IPC: H01L27/04 ,  G03F7/004 ,  H01L21/027 ,  H01L21/329 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/861

Abstract: PROBLEM TO BE SOLVED: To suppress a heat runway and improve stability of an ESD-inhibiting device in conjunction with a device scaling, by forming an in-plant under a shallow trench separation part of an ESD device. SOLUTION: An in-plant is formed under a trench separation structure of an ESD(Electrostatic Discharge) device. The in-plant is formed using a hybrid- resist. The hybrid resist formed the in-plant without any additional treatment such as mask-step. An ESD structure of a water part 2100 provides an ESD- inhibiting device function by connecting its input to the ESD device. A P++ diffusion part 2908 and an N-well 2920 constitute the first diode, and the P++ diffusion part 2908 becomes an anode and the N-well 2920 a cathode. Similarly, an N++ diffusion part 2904 and an N-well 2922 which are combined form a cathode of the second diode, and a P-type board becomes an anode.

公开(公告)号：JP2006339643A

公开(公告)日：2006-12-14

申请号：JP2006148898

申请日：2006-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ADKISSON JAMES W ,  JAFFE MARK D ,  LEIDY ROBERT K

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

Abstract: PROBLEM TO BE SOLVED: To provide an isolation structure used to isolate a pixel sensor device including a selectively doped sidewall.
SOLUTION: A new pixel sensor structure formed on a first conductive-type substrate includes a second conductive-type photosensitive device and a first conductive-type surface pinning layer 180a. The isolation structure 101a is formed adjacent to a photosensitive device pinning layer. The isolation structure includes a dopant region containing a first conductive-type material selectively formed along sidewalls 105a, 105b of the isolation structure where the surface pinning layer is adapted so as to electrically connected to a substrate 150 located beneath. A suitable method for forming the dopant region selectively formed along the sidewall of the isolation structure includes an externally diffusing process that the dopant material present in a material layer formed and doped along a selected portion of the isolation structure is driven into the substrate located beneath during annealing.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于隔离包括选择性掺杂侧壁的像素传感器装置的隔离结构。 解决方案：形成在第一导电型衬底上的新的像素传感器结构包括第二导电型光敏器件和第一导电型表面钉扎层180a。 隔离结构101a形成在与感光装置钉扎层相邻的位置。 隔离结构包括掺杂区域，该掺杂剂区域包含选择性地沿隔离结构的侧壁105a，105b形成的第一导电型材料，其中表面钉扎层适于电连接到位于下面的基底150。 用于形成沿着隔离结构的侧壁选择性形成的掺杂剂区域的合适方法包括外部扩散过程，其中存在于沿着隔离结构的选定部分形成并掺杂的材料层中的掺杂剂材料被驱动到位于下面的衬底中 退火。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11330384A

公开(公告)日：1999-11-30

申请号：JP20197998

申请日：1998-07-16

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  LEIDY ROBERT K ,  STEPHEN H BALDEMAN

IPC: G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/336 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enhance a CMOS device in latch up resistance, by a method wherein a side wall spacer/trough region is demarcated and formed by the use of hybrid photoresist which shows a positive-type, a negative type and an intermediate-type reaction to exposure light. SOLUTION: A gate oxide layer 2404 and a gate material layer 2406 are successively deposited on a wafer 2500, and side wall spacer troughs 2801 and 2802 are provided to the gate oxide layer 2404 and the gate material layer 2406 by the use of hybrid photoresist which shows a positive-type, a negative- type, and an intermediate-type reaction to exposure light. Three regions, a gate region 2804, a high source region 2806, and a high drain region 2808 are provided to the side wall spacer troughs 2801 and 2802, and a residual negative- type pattern 2526 and a residual hard mask layer 2408 are formed. By this setup, a CMOS device can be improved in latch-up resistance.