公开(公告)号：JP2006148093A

公开(公告)日：2006-06-08

申请号：JP2005319160

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  MARK C HEIKY ,  FURUKAWA TOSHIHARU ,  DAVID V HOLLACK

IPC: H01L21/027 ,  G03F7/20

CPC classification number: G03F7/70341 ,  G03F7/70925

Abstract: PROBLEM TO BE SOLVED: To remove smearing residue in an immersion lithography system. SOLUTION: The equipment for cleaning a semiconductor substrate comprises a chamber having an upper portion, a sidewall and a bottom opening where the upper portion is transparent to light of selected wavelength, an inlet and an outlet provided in the sidewall of the chamber, a plate extending outward from the bottom edge of the chamber, a set of concentric grooves formed in the bottom face of the plate and centering on the chamber, a means for applying vacuum to first and fourth grooves closest to the bottom opening of the chamber in the set of grooves, a means for supplying inert gas or vapor mixture of inert gas and solvent to a second groove between the first and fourth grooves and a fifth groove on the outside of the fourth groove in the set of grooves, and a means for supplying cleaning fluid to a third groove between the second and fourth grooves in the set of grooves. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：去除浸没式光刻系统中的污渍残留物。 解决方案：用于清洁半导体衬底的设备包括具有上部，侧壁和底部开口的室，其中上部对于所选波长的光是透明的，入口和出口设置在室的侧壁中 ，从所述室的底部边缘向外延伸的板，形成在所述板的底面中并且以所述室为中心的一组同心槽，用于对最靠近所述室的底部开口的第一和第四凹槽施加真空的装置 在一组凹槽中，用于将惰性气体或惰性气体和溶剂的惰性气体或蒸汽混合物供应到第一和第四凹槽之间的第二凹槽和该组凹槽中的第四凹槽的外侧上的第五凹槽的装置， 用于将清洁流体供应到所述一组凹槽中的第二和第四凹槽之间的第三凹槽。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH11150182A

公开(公告)日：1999-06-02

申请号：JP25779198

申请日：1998-09-11

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEVEN J HOLMS ,  DAVID V HOLLACK ,  PAUL A RABIDOU

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To enable actual method for manufacturing an SOI device and a non-SOI device on one wafer, by forming an embedded injection region between stress interface regions formed in a wafer substrate, annealing a wafer, and covering the embedded injection reign into a separation region. SOLUTION: A wafer structure 300 comprises a substrate 310 and a stress interface region 320. The stress interface region 320 is formed by etching the surface of a wafer, oxidizing a layer, growing or sticking an oxide in the etched region, and polishing the surface of wafer. In addition, a displacement region 610 formed on an injection region and an embedded oxide region 620 are provided. The stress interface region 320 absorbs stresses which are normally related to a border between an SOI region and a non-SOI region, on the surface of the wafer structure 300, for enabling manufacture of both an SOI device and a non-SOI device, with allowable level of reliability.

公开(公告)号：JP2006148092A

公开(公告)日：2006-06-08

申请号：JP2005319158

申请日：2005-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  CORLISS DANIEL A ,  DAVID V HOLLACK ,  KOBURGER CHARLES W

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/683

CPC classification number: G03F7/707 ,  G03F7/70341 ,  G03F7/70808

Abstract: PROBLEM TO BE SOLVED: To provide a method and equipment in which the possibility of bringing immersion fluid from a clearance or other portion of a chuck onto the surface of a photoresist layer on a wafer is not high. SOLUTION: Equipment for holding a wafer and a method for immersion lithography. The equipment comprises a wafer chuck having a central circular vacuum platen, an outside region, and a circular groove centering on the vacuum platen. Upper surface of the vacuum platen is recessed below the upper surface of the outside region, and the layer surface of the groove is recessed below the upper part of the vacuum platen, one or more suction ports are provided in the lower surface of the groove, and a hollow toroidal bladder capable of expansion or contraction is arranged in the groove. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种方法和设备，其中将来自夹盘的间隙或其他部分的浸没流体的可能性提供到晶片上的光致抗蚀剂层的表面上的可能性不高。

解决方案：用于保持晶片的设备和浸没式光刻方法。 该设备包括具有中心圆形真空压板，外部区域和以真空压板为中心的圆形槽的晶片卡盘。 真空压板的上表面在外部区域的上表面下方凹陷，并且凹槽的表面凹陷在真空压板的上部下方，在凹槽的下表面中设置一个或多个吸入口， 并且在槽中布置能够膨胀或收缩的空心环形囊。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006210927A

公开(公告)日：2006-08-10

申请号：JP2006018863

申请日：2006-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  STEVEN J HOLMES ,  DAVID V HOLLACK ,  KOBURGER CHARLES W III

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  B82Y10/00 ,  H01L21/28114 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a filled isolation region of a semiconductor substrate, and to provide a method of forming a semiconductor device, having the filled isolation region and cooling the device and giving body potential control. SOLUTION: A semiconductor structure and a method of forming the semiconductor structure are disclosed. The semiconductor structure includes a nanostructure or is manufactured by using the nanostructure. The method of forming the semiconductor structure includes the steps of generating the nanostructure, by using a nano mask and performing an additional semiconductor processing step by using the nanostructure thus generated. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种形成半导体衬底的填充隔离区域的改进方法，并且提供一种形成半导体器件的方法，其具有填充的隔离区域并冷却器件并给出电位控制。 解决方案：公开了半导体结构和形成半导体结构的方法。 半导体结构包括纳米结构或通过使用纳米结构制造。 形成半导体结构的方法包括以下步骤：通过使用纳米掩模产生纳米结构，并通过使用如此生成的纳米结构进行附加的半导体加工步骤。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005197736A

公开(公告)日：2005-07-21

申请号：JP2005000225

申请日：2005-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  MARK C HEIKY ,  DAVID V HOLLACK ,  KOBURGER CHARLES W III ,  MITCHELL PETER H ,  NESBIT LARRY A

IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L51/30

CPC classification number: H01L51/057 ,  B82Y10/00 ,  H01L51/0048

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a field effect transistor having a channel length controlled favorably by applying a carbon nanotube. SOLUTION: The field effect transistor employs the vertically oriented carbon nanotube as a transistor body, the carbon nanotube being formed by deposition within a vertical aperture, with an optional combination of several parallel nanotubes to produce quantized current drive, and an optional change in a chemical composition of a carbon material at the top or at the bottom to suppress short channel effect. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种形成通过施加碳纳米管有利地控制沟道长度的场效应晶体管的方法。 解决方案：场效应晶体管采用垂直取向的碳纳米管作为晶体管体，碳纳米管通过在垂直孔内沉积而形成，并且可选地组合几根平行的纳米管以产生量化电流驱动，并且可选地改变 在顶部或底部的碳材料的化学组成中抑制短沟道效应。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11330384A

公开(公告)日：1999-11-30

申请号：JP20197998

申请日：1998-07-16

Applicant: IBM

Inventor： JEFFREY S BROWN ,  JAMES S DUNE ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  LEIDY ROBERT K ,  STEPHEN H BALDEMAN

IPC: G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/336 ,  H01L27/08 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enhance a CMOS device in latch up resistance, by a method wherein a side wall spacer/trough region is demarcated and formed by the use of hybrid photoresist which shows a positive-type, a negative type and an intermediate-type reaction to exposure light. SOLUTION: A gate oxide layer 2404 and a gate material layer 2406 are successively deposited on a wafer 2500, and side wall spacer troughs 2801 and 2802 are provided to the gate oxide layer 2404 and the gate material layer 2406 by the use of hybrid photoresist which shows a positive-type, a negative- type, and an intermediate-type reaction to exposure light. Three regions, a gate region 2804, a high source region 2806, and a high drain region 2808 are provided to the side wall spacer troughs 2801 and 2802, and a residual negative- type pattern 2526 and a residual hard mask layer 2408 are formed. By this setup, a CMOS device can be improved in latch-up resistance.

公开(公告)号：JPH11274478A

公开(公告)日：1999-10-08

申请号：JP2893699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： FURUKAWA TOSHIHARU ,  MARK C HAKEY ,  STEPHEN J HORMES ,  DAVID V HOLLACK ,  WILLIAM H MA ,  MANDELMAN JACK A

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2255 ,  H01L29/66621 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element reducing a short channel effect. SOLUTION: An element has a trench 370 formed in a silicon substrate 305. The channel 380 of the element is formed on the bottom portion of the trench 370. Diffusion layers 310, 320 are formed adjacently to both sides of the trench 370 and are extended along the side walls of the trench 370 and under a part of the trench 370 to form diffusion extension parts 315, 325, whereby each diffusion layer is connected to each edge of the element channel.

Abstract translation: 要解决的问题：提供减少短通道效应的半导体元件。 解决方案：元件具有形成在硅衬底305中的沟槽370.元件的沟道380形成在沟槽370的底部上。扩散层310,320形成在沟槽370的两侧相邻并且延伸 沿着沟槽370的侧壁并在沟槽370的一部分之下形成扩散延伸部分315,325，由此每个扩散层连接到元件沟道的每个边缘。