公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000332101A

公开(公告)日：2000-11-30

申请号：JP2000131432

申请日：2000-04-28

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  BRYANT ANDRES ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator(SOI) element having both an element which is completely depleted and an element which is partially depleted on a common substrate. SOLUTION: The semiconductor structure which has a continuous buried oxide layer 24 and multiple trench separate structures 33 and 35 and its formation are disclosed. The buried oxide layer is arranged in the substrate at >=2 trench separate structures in depth. The trench separate structures are variable in depth and it is not important whether the trench separate structures are in contact with the buried oxide layer or not. The two trench separate structures enter the substrate to the same or different depths. The trench separate structures provide insulating separation between areas in the substrate and the separated areas may include a semiconductor element. The semiconductor structure makes it easy to provide a digital element and an analog element on a common wafer. The dual-depth buried oxide layer facilitates the formation of an asymmetrical semiconductor structure.

公开(公告)号：JP2001298188A

公开(公告)日：2001-10-26

申请号：JP2001083621

申请日：2001-03-22

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  FURKAY STEPHEN SCOTT ,  GAUTHIER ROBERT J JR ,  MARTIN DALE WARNER ,  SLINKMAN JAMES ALBERT

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To provide an FET where an inverse short channel effect is reduced as well as a method for forming it. SOLUTION: Germanium is so implanted over the entire semiconductor substrate at an appropriate intensity and quantity that a peak ion concentration is generated under the source and drain of the FET. The germanium is implanted before the gate, source, and drain are formed, so an inversion short channel effect which is shown with normal FETs is reduced. The short channel effect occurring with the normal FETs is never affected by implantation of germanium.

公开(公告)号：JP2000357732A

公开(公告)日：2000-12-26

申请号：JP2000124263

申请日：2000-04-25

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for improving latch up characteristic of a semiconductor element. SOLUTION: Dual depth STI 20 is used for mutually separating wells. A trench contains a first substantially horizontal face in a first depth and a second substantially horizontal face in a second depth which is deeper than the first depth. An n-well 26 and a p-well 28 are formed on the respective sides of the trench. A heavily-doped region 18 is formed below the second substantially horizontal face of the trench in a substrate. The heaving-doped region is adjacent to the first and second wells, and the separation of the trench is extended.

公开(公告)号：SG100646A1

公开(公告)日：2003-12-26

申请号：SG200101710

申请日：2001-03-17

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  STEPHEN SCOTT FURKAY ,  ROBERT J GAUTHIER JR ,  DALE WARNER MARTIN ,  JAMES ALBERT SLINKMAN

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L29/10 ,  H01L29/167

Abstract: A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.

公开(公告)号：SG91862A1

公开(公告)日：2002-10-15

申请号：SG200002012

申请日：2000-04-10

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  STEVEN H VOLDMAN ,  RANDY WILLIAM MANN ,  ANDREAS BRYANT ,  ROBERT J GAUTHIER JR

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

公开(公告)号：SG96265A1

公开(公告)日：2003-05-23

申请号：SG200107623

申请日：2001-12-06

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  JEFFREY SCOTT BROWN ,  JEFFREY D GILBERT ,  JAMES J QUINLIVAN ,  JAMES ALBERT SLINKMAN ,  ANTHONY C SPERANZA

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/31

Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.