COPPER INTERCONNECTION OF SUB-QUARTER MICRON REDUCING DEGREE OF INFLUENCE FROM DEFECT-ENHANCING ELECTRO-MIGRATION RESISTANCE

    公开(公告)号:JPH1145887A

    公开(公告)日:1999-02-16

    申请号:JP14391498

    申请日:1998-05-26

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To form performance interconnection circuit having a high dimension of sub-half micron having enhanced processing yield and reliability by a method wherein a multilayered interconnection of a copper wire separated from each other by a dielectric insulation is formed, and a contact part with an electrical mechanism in a substrate is formed. SOLUTION: A thin layer 7 of an element, capable of forming a compound between copper and a metal which preferably has a thickness of about 100 to 600 angstroms is adhered to an arbitrarily selected layer 6, and thereafter a thin copper seed layer 8 of a thickness of about 600 to 2000 angstroms is typically stacked. A remaining copper layer 9 is electrically plated after the copper seed layer 8 to bury a groove, or the layer 8, or the layer 8 and the layer 9, may be stacked by a CVD method. Next, this substrate wafer is polished by a chemical mechanical method and all extra metals are removed from a region in which a pattern is not drawn to thereby make a flat structure.

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