公开(公告)号：JP2006203198A

公开(公告)日：2006-08-03

申请号：JP2006007461

申请日：2006-01-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV V ,  WACHNIK RICHARD A ,  TAN YUE ,  KERRY BERNSTEIN

IPC: H01L27/11 ,  H01L21/8244 ,  H01L27/10

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM memory and a microprocessor, comprising a logic portion formed on a silicon substrate and an SRAM array portion. SOLUTION: The SRAM array has a body region, where at least one pair of neighboring NFETs of the SRAM cell is linked in a leakage path diffusion region 338 under shallow source/drain region 334, the leakage path diffusion region extends from the bottom of the source/drain diffusion to an embedded oxide layer 320; and at least one pair of PFETs of the neighboring SRAM cells has a body region 336, linked in a similar leakage path diffusion region under neighboring source/drain diffusion. The logic circuit portion of the microprocessor has a floating body region and an NFET, formed in a crystal orientation SOI silicon region 330 and a PFET formed in a crystal orientation bulk silicon region, and the SRAM memory portion has an NFET, formed in the crystal orientation SOI silicon region and a PFET formed in the crystal orientation silicon region. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种SRAM存储器和微处理器，包括形成在硅衬底上的逻辑部分和SRAM阵列部分。 解决方案：SRAM阵列具有主体区域，其中SRAM单元的至少一对相邻NFET被连接在浅源/漏区334下方的泄漏路径扩散区域338中，泄漏路径扩散区域从 源/漏扩散的底部到嵌入的氧化物层320; 并且相邻SRAM单元的至少一对PFET具有主体区域336，其连接在相邻的源极/漏极扩散部下的类似泄漏路径扩散区域中。 微处理器的逻辑电路部分具有形成在晶体取向SOI硅区域330和形成于晶体取向体硅区域中的PFET的浮体区域和NFET，并且SRAM存储器部分具有形成在晶体中的NFET 取向SOI硅区域和形成在晶体取向硅区域中的PFET。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH1145887A

公开(公告)日：1999-02-16

申请号：JP14391498

申请日：1998-05-26

Applicant: IBM

Inventor： RATHORE HAZARA S ,  DALAL HORMAZDYAR M ,  PAUL S MCLAUGHLIN ,  NGUYEN DU B ,  SMITH RICHARD G ,  SWINTON ALEXANDER J ,  WACHNIK RICHARD A

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To form performance interconnection circuit having a high dimension of sub-half micron having enhanced processing yield and reliability by a method wherein a multilayered interconnection of a copper wire separated from each other by a dielectric insulation is formed, and a contact part with an electrical mechanism in a substrate is formed. SOLUTION: A thin layer 7 of an element, capable of forming a compound between copper and a metal which preferably has a thickness of about 100 to 600 angstroms is adhered to an arbitrarily selected layer 6, and thereafter a thin copper seed layer 8 of a thickness of about 600 to 2000 angstroms is typically stacked. A remaining copper layer 9 is electrically plated after the copper seed layer 8 to bury a groove, or the layer 8, or the layer 8 and the layer 9, may be stacked by a CVD method. Next, this substrate wafer is polished by a chemical mechanical method and all extra metals are removed from a region in which a pattern is not drawn to thereby make a flat structure.

公开(公告)号：DE69836114D1

公开(公告)日：2006-11-23

申请号：DE69836114

申请日：1998-05-08

Applicant: IBM

Inventor： ASHLEY LEON ,  DALAL HORMAZDYAR M ,  NGUYEN DU BINH ,  RATHORE HAZARA S ,  SMITH RICHARD G ,  SWINTON ALEXANDER J ,  WACHNIK RICHARD A

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

公开(公告)号：DE69836114T2

公开(公告)日：2007-04-19

申请号：DE69836114

申请日：1998-05-08

Applicant: IBM

Inventor： ASHLEY LEON ,  DALAL HORMAZDYAR M ,  NGUYEN DU BINH ,  RATHORE HAZARA S ,  SMITH RICHARD G ,  SWINTON ALEXANDER J ,  WACHNIK RICHARD A

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.