公开(公告)号：JP2001051293A

公开(公告)日：2001-02-23

申请号：JP21460399

申请日：1999-07-29

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  MIYAMOTO TAKASHI ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO

IPC: G09F9/30 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1365 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To reduce the number of necessary processes in the manufacturing processes of thin-film transistors, and also to prevent an abnormal potential from occurring by the cause of current leaking from data lines. SOLUTION: This transistor is mounted on a prescribed substrate and is also provide with a gate electrode 30 formed in a prescribed pattern, a semiconductor layer formed corresponding to the patterning of the gate electrode 30, a pixel electrode 25 formed via this semiconductor layer, and a signal electrode formed via the semiconductor layer and also arranged with a prescribed gap from the pixel electrode 25. Then, this signal electrode is arranged at such a position that crosstalk current is prevented from flowing into the pixel electrode 25 from adjacent signal lines 32b, 32c via the semiconductor layer.

公开(公告)号：JP2002237594A

公开(公告)日：2002-08-23

申请号：JP2001027029

申请日：2001-02-02

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  HASUMI TARO ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO

IPC: G02F1/1368 ,  H01L21/28 ,  H01L21/306 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a thin-film transistor using a interlayer polymer resin, in which the self-alignment of contact holes are improved and the number of manufacturing steps can be reduced, and to provide a method for manufacturing the same and a display device including the thin-film transistor. SOLUTION: The thin-film semiconductor device includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a channel protective film 24, a source and a drain electrodes 25 and 26 respectively, a passivation layer 27 on which a first opening is formed to form a contact hole 28, and a interlayer insulating film 31 which extends along the layer 27 and has a second opening formed thereon to form the contact hole 28. The first and second openings are self-aligned to each other over a substrate 20. Conductive layers 32 and 33 are deposited on the inner wall of the contact hole 28, and the inner wall is formed by a plurality of different etching processes.

公开(公告)号：JP2000235190A

公开(公告)日：2000-08-29

申请号：JP3422799

申请日：1999-02-12

Applicant: IBM

Inventor： TOKUHIRO OSAMU ,  UEDA HIROYUKI

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To remove an etching stopper layer existing on the crossing section of a gate line and a signal line without increasing the exposure processes and to decrease the number of processes, especially the number of exposure processes by forming one or plural openings on the crossing section. SOLUTION: A gate electrode 4 and a gate line 5 integrally connected to the gate electrode 4 are formed on a light-transmitting substrate 2. Two rectangular slit-like openings 5b are formed at the section 5a (crossing section) where the gate line 5 crosses a signal line through an insulating layer. When an etching stopper 12 in the almost same form as a photoresist, namely in the almost same form as the gate electrode 4 and gate line 5, is to be formed by wet etching, the etching stopper layer 12 is removed from the crossing section 5a where the openings 5b are formed by the side-etching effect that the etching stopper 12 is etched in the width direction.

公开(公告)号：JP2003042896A

公开(公告)日：2003-02-13

申请号：JP2001202698

申请日：2001-07-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： TOKUHIRO OSAMU ,  MIWA KOICHI ,  FURUMOTO KATSUYUKI

IPC: G01R27/26 ,  G01M11/00 ,  G02F1/13 ,  G02F1/133 ,  G09F9/00

Abstract: PROBLEM TO BE SOLVED: To provide a technology for accurately evaluating the parasitic capacitance ratio accompanying with individual pixels.
SOLUTION: The apparatus comprises a signal feeder 4 for outputting a voltage signal controlled by a controller 8 to be fed to pixel electrodes; a light intensity detector 5 for detecting the light intensity of a part corresponding to the pixel electrodes on a liquid crystal cell substrate 2; and a computer 31 having a CPU for obtaining the variation quantity of the pixel voltage, based on the variation of the light intensity of the pixel electrode corresponding part detected by the detector 5, when a switching element is set from the ON state to the OFF state for controlling whether the voltage signal is fed to the pixel electrodes. The ratio of a parasitic capacitance of the pixel to the total capacitance is obtained from the variation of the pixel voltage obtained by the computer 31.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于精确评估伴随各个像素的寄生电容比的技术。 解决方案：该装置包括：信号馈送器4，用于输出由控制器8控制的电压信号以供给像素电极; 用于检测与液晶单元基板2上的像素电极对应的部分的光强度的光强度检测器5; 以及计算机31，具有CPU，用于当开关元件从接通状态设置为OFF时，基于由检测器5检测到的像素电极对应部分的光强度的变化来获得像素电压的变化量 用于控制电压信号是否馈送到像素电极的状态。 从计算机31得到的像素电压的变化，求出像素的寄生电容与总电容的比。

公开(公告)号：JP2001196591A

公开(公告)日：2001-07-19

申请号：JP2000004301

申请日：2000-01-13

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO ,  MIYAMOTO TAKASHI

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To reduce leakage current at a floating island formed on a thin-film transistor. SOLUTION: A source electrode 14 and a drain electrode 15, provided above an insulating substrate 11 at a prescribed interval, an a-Si film 16 provided to them, a gate insulating film 17 stacked on the a-Si film 16, and a gate electrode 18 stacked on the gate insulating film 17, are provided. The a-Si film 16 comprises a floating inland 20, which is not present above and below the gate electrode 18, while being present between the source electrode 14 and the drain electrode 15. The boron ion is implanted in the region, to form a boron ion implantation region 19.

公开(公告)号：JP2001077366A

公开(公告)日：2001-03-23

申请号：JP23392099

申请日：1999-08-20

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MIYAMOTO TAKASHI ,  MOROOKA MITSUO

IPC: H01L21/205 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  G02F1/1365

Abstract: PROBLEM TO BE SOLVED: To improve productivity in the deposition of the a-Si film of a thin film transistor and also enhance the thin film transistor in characteristics. SOLUTION: An amorphous silicon film 2, a gate insulating film 3, a gate insulating film 3, and a gate electrode 4 are sequentially laminated on an insulating substrate 1 for the formation of a thin film transistor. In this case, the amorphous silicon film 2 is composed of a low-defect density amorphous silicon layer 5 that is formed at a low deposition rate and a high-speed amorphous silicon layer 6 formed at a higher deposition rate than the silicon layer 5, where the amorphous silicon layer 5 is located closer to the insulating board 1 than the amorphous silicon layer 6, and the amorphous silicon layer 6 is formed coming into contact with the under surface of the gate insulating film 3.

公开(公告)号：JP2002043575A

公开(公告)日：2002-02-08

申请号：JP2000208593

申请日：2000-07-10

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MIWA KOICHI ,  MOROOKA MITSUO

IPC: G02F1/1333 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of an active matrix substrate by preventing the corrosion, etc., of lead-out wiring by covering the wiring with a gate insulating film or ITO without adding any patterning process and, in addition, improving the manufacturing yield of the substrate. SOLUTION: This active matrix substrate is provided with a source electrode 14 and a drain electrode 15 which are arranged above an insulating substrate 11 with a prescribed clearance in between; an a-Si film 17, a gate insulating film 18, and a gate electrode 19 successively laminated upon the electrodes 14 and 15; and an ITO 20 having a first portion which is laminated upon the gate electrode 19 and has the same patterned surface as the electrode 19 has and a second portion which is formed to partially cover the source electrode 14 and forms a picture element electrode. The substrate is also provided with a data line 16 which is connected to the drain electrode 15 and covered with another gate insulating film 18.

公开(公告)号：JP2001338880A

公开(公告)日：2001-12-07

申请号：JP2000156007

申请日：2000-05-26

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO ,  MIYAMOTO TAKASHI

IPC: G02F1/136 ,  C23C16/44 ,  G02F1/1368 ,  G09F9/00 ,  H01L21/00 ,  H01L21/205 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method and device that can improve productivity, and can reduce costs for manufacturing an active matrix device including a top-gate-type TFT without poorly affecting the characteristics of the TFT. SOLUTION: This method includes a process that forms oxide coating 15 on the internal wall of a treatment chamber 9 for CVD in the manufacture of the top-gate-type TFT, a process that arranges a substrate 1 where source and drain electrodes 5 and 4 are formed in the treatment chamber 9, a process that carries out P doping to the source and drain electrodes 5 and 4, and a process that forms an a-Si layer 6 and a gate insulating film 7 in the treatment chamber. Also, this device manufactures the active matrix device including the top-gage-type TFT where the inner surface of the treatment chamber 9 is coated with the oxide coating 15.

公开(公告)号：JP2001337051A

公开(公告)日：2001-12-07

申请号：JP2000157500

申请日：2000-05-29

Applicant: AITESU KK ,  IBM

Inventor： MIYAZAKI YOSHIHIRO ,  FURUMOTO KATSUYUKI ,  TOKUHIRO OSAMU ,  NAKAMURA KAZUHIKO

IPC: G01R1/073 ,  G01M11/00 ,  G01N21/958 ,  G02F1/13 ,  G02F1/1335 ,  G02F1/13357 ,  G09F9/00

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and a method for inspecting substrate products and a probe for inspection whereby whether or not substrate products are good can be easily inspected. SOLUTION: This substrate product-inspecting apparatus 10 is constituted of a signal generator 16 for applying voltage signals to the liquid crystal cell substrate 14, a light source 17 for illuminating the liquid crystal cell substrate 14 with light, a detector 18 for detecting an output light formed when the light of the light source 17 passes the liquid crystal cell substrate 14 or is reflected by the substrate 14, and a computer 24 for detecting signals of the detector 18.

公开(公告)号：JP2000114532A

公开(公告)日：2000-04-21

申请号：JP27868998

申请日：1998-09-30

Applicant: IBM ,  TOSHIBA CORP

Inventor： TOKUHIRO OSAMU ,  UEDA HIROYUKI ,  MACHIDA MASAHIKO

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve product yield and quality of a liquid-crystal display panel by, related to a method for manufacturing a liquid-crystal display panel, decreasing the number of processes, especially for exposure process, for improved productivity and lower manufacturing cost while occurrence of transistor defect related to an etching stopper part is suppressed. SOLUTION: After a gate insulating film 6, a channel layer 8, an etching stopper layer are film-formed on a translucent substrate 2 where a gate electrode 4 is formed, the rear surface of the substrate 2 is exposed with the gate electrode 4 as a light-shielding mask by a photolithography technology, a resist is developed as it is, and the etching stopper layer is etched to form an etching stopper 14. Further, after a source/drain layer is film-formed, the remaining parts of the source/drain layer and the etching stopper are etched by a chemical vapor-phase etching.