公开(公告)号：BR112022021777A2

公开(公告)日：2022-12-13

申请号：BR112022021777

申请日：2021-04-30

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: H01L29/78 ,  H01L21/336

Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

公开(公告)号：IL298029B1

公开(公告)日：2025-05-01

申请号：IL29802922

申请日：2022-11-07

Applicant: IBM CORP ,  TAO LI ,  TSUNG SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

Inventor： TAO LI ,  TSUNG-SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D64/23 ,  H10D64/62

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

公开(公告)号：IL298029A

公开(公告)日：2023-01-01

申请号：IL29802922

申请日：2022-11-07

Applicant: IBM CORP ,  TAO LI ,  TSUNG SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

Inventor： TAO LI ,  TSUNG-SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

公开(公告)号：IL297096A

公开(公告)日：2022-12-01

申请号：IL29709622

申请日：2022-10-06

Applicant: IBM ,  RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG SHENG KANG

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: B82Y10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：IL295107A

公开(公告)日：2022-09-01

申请号：IL29510722

申请日：2022-07-26

Applicant: IBM ,  TSUNG SHENG KANG ,  ARDASHEIR RAHMAN ,  PRAVEEN JOSEPH ,  INDIRA SESHADRI ,  EKMINI ANUJA DE SILVA ,  TAO LI

Inventor： TSUNG-SHENG KANG ,  ARDASHEIR RAHMAN ,  PRAVEEN JOSEPH ,  INDIRA SESHADRI ,  EKMINI ANUJA DE SILVA ,  TAO LI

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.