公开(公告)号：BR112022021777A2

公开(公告)日：2022-12-13

申请号：BR112022021777

申请日：2021-04-30

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: H01L29/78 ,  H01L21/336

Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

公开(公告)号：GB2600316B

公开(公告)日：2023-05-24

申请号：GB202200795

申请日：2020-06-15

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

公开(公告)号：GB2635490A

公开(公告)日：2025-05-14

申请号：GB202504146

申请日：2023-05-18

Applicant: IBM

Inventor： JUNTAO LI ,  KANGGUO CHENG ,  CARL RADENS ,  CHING-TZU CHEN

IPC: H10N70/20 ,  H10B63/10

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

公开(公告)号：IL297096A

公开(公告)日：2022-12-01

申请号：IL29709622

申请日：2022-10-06

Applicant: IBM ,  RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG SHENG KANG

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: B82Y10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：GB2600316A

公开(公告)日：2022-04-27

申请号：GB202200795

申请日：2020-06-15

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  VEERARAGHAVAN BASKER

IPC: H01L29/00 ,  H10B10/00

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.