公开(公告)号：BR112022021777A2

公开(公告)日：2022-12-13

申请号：BR112022021777

申请日：2021-04-30

Applicant: IBM

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: H01L29/78 ,  H01L21/336

Abstract: TRANSISTOR DE NANOFOLHAS COM PILHA DE PORTA ASSIMÉTRICA. Métodos e estruturas resultantes para dispositivos de nanofolhas com pilhas de portas assimétricas são descritos. Uma pilha de nanofolhas (102) é formada sobre um substrato (104). A pilha de nanofolhas (102) inclui camadas semicondutoras alternadas (108) e camadas de sacrifício (110). Um revestimento de sacrifício (202) é formado sobre a pilha de nanofolhas (102) e uma estrutura de porta dielétrica (204) é formada sobre a pilha de nanofolhas (102) e o revestimento de sacrifício (202). Um primeiro espaçador interno (302) é formado em uma parede lateral das camadas de sacrifício (110). Uma porta (112) é formada sobre regiões de canal da pilha de nanofolhas (102). A porta (112) inclui uma ponte condutora que se estende sobre o substrato (104) em uma direção ortogonal à pilha de nanofolhas (102). Um segundo espaçador interno (902) é formado em uma parede lateral do portão (112). O primeiro espaçador interno (302) é formado antes da pilha de portas (112), enquanto o segundo espaçador interno (902) é formado depois e, consequentemente, a pilha de portas (112) é assimétrica.

公开(公告)号：GB2627627B

公开(公告)日：2025-04-02

申请号：GB202407430

申请日：2022-11-23

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  JUNLI WANG ,  DECHAO GUO ,  RUQIANG BAO ,  RISHIKESH KRISHNAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN

IPC: H10D84/01 ,  H01L23/528 ,  H10D30/01 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/03 ,  H10D84/85 ,  H10D88/00

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

公开(公告)号：GB2632937A

公开(公告)日：2025-02-26

申请号：GB202414140

申请日：2023-02-10

Applicant: IBM

Inventor： RUILONG XIE ,  NICOLAS JEAN LOUBET ,  JULIEN FROUGIER ,  DECHAO GUO

IPC: H10D88/00 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A semiconductor structure including a first stacked transistor structure including a top device stacked directly above a bottom device, and a second stacked transistor structure adjacent to the first stacked transistor, the second stacked transistor including a top device stacked directly above a bottom device, where the top device of the first stacked transistor structure and the top device of the second stacked transistor structure are made from different gate dielectric materials, and where the bottom device of the first stacked transistor structure and the bottom device of the second stacked transistor structure are made from different gate dielectric materials.

公开(公告)号：GB2627706B

公开(公告)日：2024-12-11

申请号：GB202408528

申请日：2022-11-28

Applicant: IBM

Inventor： CHEN ZHANG ,  RUILONG XIE ,  JUNLI WANG ,  DECHAO GUO

IPC: G06F15/16 ,  G11C11/412 ,  G11C11/417 ,  H10B10/00

Abstract: A compact SRAM design in a stacked architecture is provided. Notably, a 6-transistor SRAM bite cell including a bottom device level containing bottom field effect transistors and a top device level, stacked above the bottom device level, containing top field effect transistors of a different conductivity type than the bottom field effect transistors is provided.

公开(公告)号：IL297096A

公开(公告)日：2022-12-01

申请号：IL29709622

申请日：2022-10-06

Applicant: IBM ,  RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG SHENG KANG

Inventor： RUILONG XIE ,  CARL RADENS ,  KANGGUO CHENG ,  JUNTAO LI ,  DECHAO GUO ,  TAO LI ,  TSUNG-SHENG KANG

IPC: B82Y10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.