公开(公告)号：EP1992012A4

公开(公告)日：2011-08-17

申请号：EP07861255

申请日：2007-03-01

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  SPOONER TERRY A ,  VAN DER STRATEN OSCAR

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2020027A4

公开(公告)日：2010-12-01

申请号：EP07870667

申请日：2007-05-11

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  VAN DER STRATEN OSCAR

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/288 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2007194624A

公开(公告)日：2007-08-02

申请号：JP2006353015

申请日：2006-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MALHOTRA SANDRA G ,  DELIGIANNI HARIKLIA ,  VAN DER STRATEN OSCAR ,  SHAO XIAOYAN ,  ROSSNAGEL STEPHEN M ,  TAI TSONG-LIN

IPC: H01L23/52 ,  C23C16/16 ,  C23C16/56 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  Y10S438/952

Abstract: PROBLEM TO BE SOLVED: To provide a process for direct electroplating of copper on a platable layer which is not copper.
SOLUTION: This process for forming an interconnection in a semiconductor structure comprises a step for forming a dielectric layer on a substrate, a step for forming a first barrier layer on the dielectric layer, and a step for forming a second barrier layer on the first barrier layer. The second barrier layer is selected from a group including ruthenium, platinum, palladium, rhodium and iridium. The second barrier layer is formed by a process including a step for manipulating so that bulk concentration of oxygen in the second barrier layer becomes 20 atm.% or less, and a step for forming a conductive layer on the second barrier layer. This process further can include a step for treating the second barrier to decrease the amount of an oxide on the surface of the second barrier layer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在不是铜的可镀层上直接电镀铜的方法。 解决方案：用于在半导体结构中形成互连的该工艺包括在衬底上形成电介质层的步骤，在电介质层上形成第一阻挡层的步骤和用于形成第二阻挡层的步骤 第一阻隔层。 第二阻挡层选自包括钌，铂，钯，铑和铱的组。 第二阻挡层通过包括操作步骤的方法形成，使得第二阻挡层中的氧的体积浓度变为20atm％以下，以及在第二阻挡层上形成导电层的步骤。 该方法还可以包括用于处理第二阻挡层以减少第二阻挡层的表面上的氧化物的量的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2008069832A2

公开(公告)日：2008-06-12

申请号：PCT/US2007011437

申请日：2007-05-11

Applicant: IBM ,  YANG CHIH-CHAO ,  VAN DER STRATEN OSCAR

Inventor： YANG CHIH-CHAO ,  VAN DER STRATEN OSCAR

IPC: H01L23/52

CPC classification number: H01L21/76834 ,  H01L21/288 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.

Abstract translation: 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可存在于含Co缓冲层中。

公开(公告)号：AU2021281966A1

公开(公告)日：2022-10-27

申请号：AU2021281966

申请日：2021-04-29

Applicant: IBM

Inventor： MANISCALCO JOSEPH F ,  VAN DER STRATEN OSCAR ,  MOTOYAMA KOICHI ,  LEE CHOONGHYUN ,  KIM SEYOUNG

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

公开(公告)号：DE112021000239T5

公开(公告)日：2022-09-08

申请号：DE112021000239

申请日：2021-01-12

Applicant: IBM

Inventor： MANISCALCO JOSEPH ,  MOTOYAMA KOICHI ,  VAN DER STRATEN OSCAR ,  DEVRIES SCOTT ,  REZNICEK ALEXANDER

IPC: H01L21/768 ,  H01L23/532

Abstract: Eine Verbindungsstruktur und ein Verfahren zum Bilden selbiger umfasst Bilden einer Aussparung innerhalb einer Dielektrikumsschicht und formangepasstes Abscheiden einer Barriereschicht innerhalb der Aussparung. Über der Barriereschicht wird eine Rutheniumauskleidung mit Kobaltinfusion gebildet, wobei die Kobalt enthaltende Rutheniumauskleidung durch Stapeln einer zweiten Auskleidung über eine erste Auskleidung gebildet wird, wobei die erste Auskleidung über der Barriereschicht positioniert ist. Die erste Auskleidung umfasst Ruthenium, während die zweite Auskleidung Kobalt umfasst. Kobaltatome migrieren aus der zweiten Auskleidung in die erste Auskleidung, wodurch die Rutheniumauskleidung mit Kobaltinfusion gebildet wird. Über der Rutheniumauskleidung mit Kobaltinfusion wird ein leitfähiges Material abgeschieden, um die Aussparung zu füllen, gefolgt von einer Abdeckungsschicht, die aus Kobalt hergestellt wird.