公开(公告)号：EP2243155A4

公开(公告)日：2012-07-25

申请号：EP09705024

申请日：2009-01-22

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  EDELSTEIN DANIEL C ,  MCFEELY FENTON R

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1841558A4

公开(公告)日：2012-04-04

申请号：EP05852628

申请日：2005-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER ENAMUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00 ,  B23H5/08

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

公开(公告)号：EP2008301A4

公开(公告)日：2012-09-05

申请号：EP07760071

申请日：2007-04-04

Applicant: IBM

Inventor： EDELSTEIN DANIEL C ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  MELVILLE IAN D

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

公开(公告)号：JP2001118813A

公开(公告)日：2001-04-27

申请号：JP30089099

申请日：1999-10-22

Applicant: IBM

Inventor： BRASTA BRUSICK ,  EDELSTEIN DANIEL C ,  PAUL M FENII ,  WILLIAM GUTHRIE ,  MARK JASO ,  FRANK B KAUFFMANN ,  NAFUTARI RASUTEIGU ,  PETER LAUPER ,  RODBELL KENNETH ,  DAVID B THOMPSON

IPC: H01L21/304 ,  C09K3/14 ,  C09K13/00 ,  C09K13/02 ,  C09K13/04 ,  C09K13/06

Abstract: PROBLEM TO BE SOLVED: To speedily eliminate copper and to minimize the loss of copper in a patterned interconnected body without eliminating a metal layer and a dielectric layer at a lower side or corroding copper. SOLUTION: The chemical - mechanical polishing(CMP) slurry for polishing the layer of copper or that of the alloy of copper contains an etchant, an oxidation suppression agent, and an additive for adjusting the complexing between the copper and the oxidation suppression agent.

公开(公告)号：JP2001015464A

公开(公告)日：2001-01-19

申请号：JP2000131737

申请日：2000-04-28

Applicant: IBM

Inventor： WILLIAM J COLE ,  EDELSTEIN DANIEL C ,  NAPHTALI E LASTIG

IPC: B24B37/00 ,  C09C1/68 ,  C09G1/02 ,  C09K3/14 ,  C09K13/00 ,  C23F3/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/321 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain a CMP process which increases the removing speed of a liner for copper metallurgy composed of a metal having a high melting point, its alloy or compound, or both the metal and alloy or compound and, at the same time, can minimize the formation of recesses and erosion by removing the liner with slurry containing an oxidizing agent, a corrosion inhibitor, and a surface active agent. SOLUTION: The polishing speeds of a liner 20 and an insulator 10 are controlled so as to make the speeds faster than the polishing speed of copper 22. Namely, in order to make the condition for removing a Ta/TaN liner composed mainly of Ta from a semiconductor substrate which is passivated with silicon dioxide, the liner 20 is removed by CIVIP in acidic slurry containing an oxidizing agent, such as the hydrogen peroxide, a corrosion inhibitor, such as the demineralized water, BTA, etc., and a surface active agent, such as the Duponol SP, etc. Consequently, a CMP process which can increase the removing speed of the liner and, at the same time, can minimize the formation of recesses and erosion can be obtained.

公开(公告)号：JP2006216541A

公开(公告)日：2006-08-17

申请号：JP2006013182

申请日：2006-01-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL ,  LIN QINGHUANG ,  MILLER ROBERT D ,  NEUMAYER DEBORAH A ,  NGUYEN SON VAN

IPC: H01B3/00 ,  C23C16/42 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures. SOLUTION: The low-k dielectric material includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si-CH 3 functional groups, and another fraction of the C atoms are bonded as Si-R-Si, wherein R is phenyl, -[CH 2 ] n -, (n is greater than or equal to 1), HC=CH, C=CH 2 , C≡C or a [S] n linkage, (n is as defined above). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有增加的内聚强度的低k电介质材料，用于包括互连和感测结构的电子结构中。 解决方案：低k电介质材料包括Si，C，O和H的原子，其中C原子的一部分键合为Si-CH 3 S / S官能团，另一部分 的C原子键合为Si-R-Si，其中R是苯基， - （n大于或等于1） ，HC = CH，C = CH 2 ，C≡C或[S] n 键，（n如上所定义）。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001267356A

公开(公告)日：2001-09-28

申请号：JP2001032285

申请日：2001-02-08

Applicant: IBM

Inventor： CARLOS J SAMUBUSETTEI ,  EDELSTEIN DANIEL C ,  JOHN G GAUDEIERO ,  JUDETH M RUBINO ,  GEORGE WALKER

IPC: H05K3/34 ,  C23C18/16 ,  H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/532 ,  H05K3/24 ,  H05K13/06

Abstract: PROBLEM TO BE SOLVED: TO provide a method for preparing an electrically connected copper pad having superior diffusing barrier characteristics and bonding characteristic. SOLUTION: The method for preparing an electrically connecting conductive pad comprises the steps of first preparing a copper pad surface 14 cleaned by an acid solution, than adhering a protective layer of a phosphorus or a boron-containing metal alloy to the surface of the pad, and then adhering an adhesive layer 18 of a noble metal onto the protective layer. In this case, a suitable thickness of the protective layer is in the range of 1,000 to about 10,000 Åor preferably about 3,000 to about 7,000 Å. The adhesive layer is formed of the noble metal, such as Au, Pt, Pd, Ag or the like and can be formed into a thickness of about 500 to about 4,000 Å or preferably about 1,000 to about 2,000 Å. Or before electrolessly adhering of the protective layer, a Pd nucleating layer may be adhered between the surface of the copper conductive pad and the protective layer.

公开(公告)号：JP2006024943A

公开(公告)日：2006-01-26

申请号：JP2005199284

申请日：2005-07-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LANE MICHAEL ,  CHIRAS STEFANIE R ,  SPOONER TERRY A ,  ROSENBERG ROBERT ,  EDELSTEIN DANIEL C

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52

CPC classification number: C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a conductive material having a conductive core region containing copper and an interface region, and to provide a manufacturing method of the conductive material. SOLUTION: The conductive material comprises a conductive core region containing copper, and one or more metal selected from iridium, osmium, and rhenium in terms of atomic percentage of 0.001 to 0.6, and an interface region. The interface region contains one or more metal in terms of at least 80 atomic percentage or more. In the interface region, a seed layer containing copper, and one or more metal selected from iridium, osmium, and rhenium is formed, and a conductive layer composed of copper is formed thereon. Then, by polishing the conductive layer, a surface material of a polished copper is constituted. Thus, the conductive material is formed by annealing the polished surface material of copper at a sufficient temperature for causing migration of one or more metals from the seed layer to the polished surface. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有含铜和界面区域的导电芯区域的导电材料，并提供导电材料的制造方法。 解决方案：导电材料包括含有铜的导电芯区域和以原子百分比为0.001至0.6的选自铱，锇和铼的一种或多种金属和界面区域。 界面区域包含至少80原子百分比或更多的一种或多种金属。 在界面区域中，形成含有铜的籽晶层和选自铱，锇和铼的一种或多种金属，并且在其上形成由铜构成的导电层。 然后，通过研磨导电层，构成抛光铜的表面材料。 因此，导电材料通过在足够的温度下退火抛光的铜表面材料形成，以使一种或多种金属从晶种层向抛光表面迁移。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007115292A2

公开(公告)日：2007-10-11

申请号：PCT/US2007065929

申请日：2007-04-04

Applicant: IBM ,  EDELSTEIN DANIEL C ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  MELVILLE IAN D

Inventor： EDELSTEIN DANIEL C ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  MELVILLE IAN D

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

Abstract: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad (104) in an upper level of a semiconductor wafer (106), forming an insulating stack (114) over the terminal copper pad, and patterning and opening a terminal via (116) within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer (126) is formed and patterned over the top of the insulating stack, and the bottom cap layer (118) over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack (128) is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection (108) is formed on a patterned portion of the BLM stack.

Abstract translation: 一种用于远端（FBEOL）半导体器件形成的方法，包括在半导体晶片（106）的上层形成端子铜焊盘（104），在端子铜焊盘上形成绝缘堆叠（114） 以及在绝缘堆叠的一部分内打开端子（116），以便留下保护端子铜焊盘的绝缘堆叠的底盖层。 在绝缘堆叠的顶部上形成并图案化有机钝化层（126），并且去除端子铜焊盘上的底盖层（118）。 在有机钝化层和端子铜焊盘上沉积了极限极限冶金（BLM）堆叠（128），并且在BLM堆叠的图案化部分上形成焊球连接（108）。