公开(公告)号：JP2000156461A

公开(公告)日：2000-06-06

申请号：JP15140999

申请日：1999-05-31

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  FERENCE THOMAS GEORGE ,  WAYNE JOHN HOWEL ,  SPROGIS EDMUND J

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To individually set a chip and to achieve a compact semiconductor package with a high-integration technique by equipping a plurality of independent chips that are electrically connected and function completely and chip-on- chip part connection/interconnection for electrically connecting the chips to an external circuit. SOLUTION: Chip-on-chip parts 10 include a first chip 30, a second chip 40, and chip-on-chip part connection 20. An active region 35 of the first chip 30 is electrically connected to an active region 45 of the second chip 40 via solder ball connection 50 or electrical connection between chips. Also, the chip- on-chip part connection 20 is a solder column 22 that is connected to the first chip 30, and the solder column 22 can connect the chip-on-chip parts 10 to an external circuit via a substrate, thus achieving a reliable, compact semiconductor package with high-integration technique and at the same time improving thermal performance.

公开(公告)号：JP2000236001A

公开(公告)日：2000-08-29

申请号：JP2000005442

申请日：2000-01-14

Applicant: IBM

Inventor： JOSEPH A BENENATTI ,  WILLIAM T CHEN ,  LISA A FANTI ,  WAYNE JOHN HOWEL ,  KNICKERBOCKER JOHN U

IPC: H01L21/56 ,  H01L21/60 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To reduce thermo-kinetic fatigue to a minimum in a flip-chip package. SOLUTION: An interposer 400 used for mounting a flip-chip is made of an organic polymer which includes an aperture 33, having a conductive plug 433 and selected in a such way that an optimum length between a substrate and a chip with a coefficient of thermal expansion in matching with the extremum of a thermal cycle temperate of the module component can be obtained. The conductive plug 433 is made of a high-temperature solder 40, provided in an inside of the aperture 33 and a low-temperature solder 45 provided to the outer side of the high-temperature solder 40. Then, a low- temperature solder 45 is subjected to reflow, while the high-temperature solder becomes solid.

公开(公告)号：JPH10189873A

公开(公告)日：1998-07-21

申请号：JP32619697

申请日：1997-11-27

Applicant: IBM

Inventor： CLAUDE LOUIS BERTIEN ,  WAYNE JOHN HOWEL ,  WILLIAM ROBERT PATRICK TONTY ,  JERSEY MARIA ZARENSKI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit with a developing means of fairly effective on-chip decoupling capacitance, regardless of the density of the formed circuit. SOLUTION: This integrated high-performance decoupling capacitance, formed on a semiconductor chip 10 comprising the substrate of a chip itself junctioned with metallic attachments 34 formed on the underside of presently not yet used chip is electrically connected to an active chip circuit resultingly approaching to the active circuit on the chip requiring of such a decoupling capacitance, so as to develop a fairly effective decoupling capacitance. In such a constitution, such a development can be realized by a method, wherein a dielectric layer is provided on the underside of not yet used chip so that the metallic attachments 34 formed on the underside may be electrically connected to the active chip circuit via a through-hole 30 in the chip.