公开(公告)号：US6360938B2

公开(公告)日：2002-03-26

申请号：US79459701

申请日：2001-02-27

Applicant: IBM

Inventor： DELAURENTIS STEPHEN A ,  INTERRANTE MARIO J ,  JACKSON RAYMOND A ,  KNICKERBOCKER JOHN U ,  RAY SUDIPTA K ,  STALTER KATHLEEN A

IPC: B23K1/018 ,  H01L21/687 ,  B23K31/02

CPC classification number: H01L21/687 ,  B23K1/018

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

Abstract translation: 一种用于通过在将模块加热到足以导致的温度的温度下向一个或多个倒装芯片的背面施加张力而将一个或多个去除构件施加拉力而移除通过安装在多芯片模块上的C4接头的倒装芯片的方法和装置 C4接头变得熔化。 张力可以是压缩弹簧，也可以是在室温下为平坦的双金属构件，在加热到这样的温度时变得弯曲，或者是原始形状弯曲并在室温下弯曲平坦但是返回的记忆合金 在加热到这样的温度时变成原来的弯曲形状。 使用粘合剂将去除构件粘合到要去除的芯片上，并且是固化后具有耐高温性的低温快速固化粘合剂。

公开(公告)号：EP1587764A4

公开(公告)日：2009-04-15

申请号：EP03790042

申请日：2003-11-25

Applicant: IBM

Inventor： GOVINDARAJAN NATARAJAN ,  AHMAD UMAR ,  BEZAMA RASHID J ,  HUMENIK JAMES N ,  KNICKERBOCKER JOHN U ,  VALLABHANENI RAO V

IPC: B01L3/00 ,  B29C65/00 ,  B32B18/00 ,  C03B29/00 ,  C04B33/34 ,  C04B37/00

CPC classification number: B32B18/00 ,  B01J2219/00286 ,  B01J2219/00317 ,  B01L3/502707 ,  B01L3/5085 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/0819 ,  B01L2300/0887 ,  B01L2300/12 ,  B81B2203/0338 ,  B81B2203/0353 ,  B81C1/00119 ,  C04B35/645 ,  C04B2235/6567 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/62 ,  C04B2237/704

Abstract: A plate (10) for use in mixing and testing materials in the pharmaceutical industry is formed by a method in which apertures (22) (24) in a set of greensheets are formed by a material removal process, at least some of the apertures (25) being filled with a fugitive material (222) that escapes during sintering.

公开(公告)号：EP3028294A4

公开(公告)日：2016-10-19

申请号：EP14832804

申请日：2014-07-29

Applicant: IBM

Inventor： DANG BING ,  KNICKERBOCKER JOHN U ,  TSANG CORNELIA KANG-I

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/67132 ,  B23K26/36 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/6838 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation

Abstract translation: 提供的结构和方法用于使用包括一个或多个可使用中波长红外辐射激光可消除的可释放层的结合结构将处理器晶片临时粘合到器件晶片

公开(公告)号：JP2000357874A

公开(公告)日：2000-12-26

申请号：JP2000149183

申请日：2000-05-22

Applicant: IBM

Inventor： FASANO BENJAMIN V ,  INDYK RICHARD F ,  KAMATH SUNDAR M ,  KNICKERBOCKER JOHN U ,  LANGENTHAL SCOTT I ,  O'CONNOR DANIEL P ,  REDDY SRINIVASA S N

IPC: H05K1/11 ,  B32B18/00 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a ceramic substrate of low thermal-expansion factor by providing a plurality of layers of a multi-layer ceramic material comprising a sealing layer and a via hole which, filled with a metal material, comprises no ceramic material. SOLUTION: At a via hole part 24 of a first layer 12, a via hole 26 which, filled with a metal material, comprises no ceramic material is formed. A via hole 28 comprising a mixture of metal material and ceramic material is inserted in a second layer 14, and the via hole 28 so seals a ceramic substrate 10 not to penetrate deeper than the first layer 12. For a third layer 16, a via hole 30 comprising no ceramic material is formed related to the via hole 26 in the first layer 12. Thus, the via holes 26, 28, and 30 of the plurality of layers 12, 14, and 16 allows transmission of electric signal and power between layers, sealing an outside part layer 20 with a via hole 38.

公开(公告)号：JP2008172223A

公开(公告)日：2008-07-24

申请号：JP2007330072

申请日：2007-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KNICKERBOCKER JOHN U ,  HARIKLIA DELIGIANNI ,  BASKER VEERARAGHAVAN S ,  JOHN MICHAEL COTT ,  KWIETNIAK KEITH T

IPC: H01L23/32 ,  H01L23/14

CPC classification number: H01L23/433 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/481 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carrier, having a conductive through-via for achieving the high yield manufacturing of a silicon carrier with low defect density. SOLUTION: This silicon carrier 43 is formed with via diameters, ranging from one micron to 10 microns, with respect to vertical thickness ranging from 10 microns or smallers to 300 microns or larger. Thus, it is possible to manufacture a silicon carrier which is resistant to a thermal mechanical stresses, when manufacturing, and significant minimization of its thermal mechanical movement on a via side wall interface among silicon materials, insulator materials, linear materials and conductive materials is effected. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造硅载体的方法，具有用于实现低缺陷密度的硅载体的高产率制造的导电通孔。 解决方案：相对于10微米或更小至300微米或更大的垂直厚度，该硅载体43的通孔直径为1微米至10微米。 因此，可以制造耐热机械应力的硅载体，当制造时，并且在硅材料，绝缘体材料，线性材料和导电材料之间的通孔侧壁界面上的热机械运动的显着最小化被实现 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008042904A

公开(公告)日：2008-02-21

申请号：JP2007195973

申请日：2007-07-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NILS DENEKE HOIVIK ,  JOHN MICHAEL COTT ,  KNICKERBOCKER JOHN U ,  GAUCHER BRIAN P ,  JANUSZ GRZYB ,  CHRISTOPHER VINCENT JAHNES ,  JOHN HAROLD MAGERLEIN ,  CHIRAG SURYAKANT PATEL ,  DUIXIAN LIU ,  PFEIFFER ULLRICH R ,  TSANG CORNELIA KANG-I

IPC: H01Q19/06 ,  H01L23/12 ,  H01L23/14 ,  H01L25/00 ,  H01Q19/10 ,  H01Q19/12

CPC classification number: H01L25/165 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/162 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01L2924/00 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a Si-based packaging with integrated passive components for millimeter wave applications. SOLUTION: An apparatus is described incorporating an interposer 1 having a cavity for a portion of an antenna structure 22, having conductor through vias 3, a top Si part 6 having interconnection wiring 72, 73, 74 and having pads for electrically mounting an integrated circuit chip 21 thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and the top Si part may be scaled to provide an array of functional units. This invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于毫米波应用的集成无源组件的Si基封装。 解决方案：描述一种装置，其包括具有用于天线结构22的一部分的腔的插入器1，其具有导体穿过通孔3，顶部Si部分6具有互连布线72,73,74并具有用于电安装的垫 其上的集成电路芯片21，其中顶部Si部件电气和机械地与插入器配合。 插入器和顶部Si部分可以被缩放以提供功能单元的阵列。 本发明克服了将高效率天线与Si封装中的集成电路芯片组合在一起的信号频率为1至100GHz的问题，以及屏蔽靠近天线的组件的问题，并减少了由于TCE失配引起的应变。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007294959A

公开(公告)日：2007-11-08

申请号：JP2007105961

申请日：2007-04-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STEVEN ALAN CORDES ,  SPEIDELL JAMES L ,  GRUBER PETER ALFRED ,  KNICKERBOCKER JOHN U

IPC: H01L21/60 ,  B23K3/06

CPC classification number: B23K3/0638 ,  B23K35/02 ,  B23K2201/40 ,  H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for injection molding of conductive bonding material to a plurality of cavities of a non-rectangular mold. SOLUTION: This method includes aligning a filling head with the non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The filling head is arranged so as to substantially contact the non-rectangular mold. Rotational motion is given to at least any one of the non-rectangular mode and the filling head in a state where the filling head substantially contacts the non-rectangular mold. The conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided to at least any one of the plurality of cavities simultaneously with the approximation of at least the one cavity to the filling head. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于将导电接合材料注射成型到非矩形模具的多个空腔的系统和方法。

解决方案：该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被布置成基本接触非矩形模具。 在填充头基本上接触非矩形模具的状态下，对非矩形模式和填充头中的至少任何一个进行旋转运动。 导电接合材料被迫从非矩形模具中排出填料头。 导电接合材料被提供到多个空腔中的至少任一个同时与至少一个空腔近似到填充头。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004139041A

公开(公告)日：2004-05-13

申请号：JP2003313303

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHRISTOPH BERGER ,  KNICKERBOCKER JOHN U ,  EMMA PHILIP G ,  DECUSATIS CASIMER M ,  BROOKS CAMERON ,  JACOBOWITZ LAWRENCE

IPC: G02B6/10 ,  G02B6/122 ,  G02B6/28 ,  G02B6/30 ,  G02B6/34 ,  G02B6/38 ,  G02B6/43 ,  H04B10/02 ,  H04B10/12

CPC classification number: G02B6/30 ,  G02B6/2826 ,  G02B6/3817 ,  G02B6/3829 ,  G02B6/3839 ,  G02B6/43

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for forming a step-like construction for connection of optical waveguides between a card and a backplane. SOLUTION: Optical waveguides 20 and conductors are embedded in a card 10, and ends 45 terminating at the step-like construction exist therein. Optical fiber ribbons 50 project from the ends 45. Also, a guide structure 60 is connected to the ends 45. The guide structure 60 has grooves for guiding and aligning the ribbons 50. Optical waveguides 25 and conductors are embedded in a backplane 70 as well, and have ends 75 terminating at the step-like construction and an aperture 90 having a slope. A guide structure 80 is connected to the ends 75. The aperture 90 having the slope accepts and guides the ribbons 50 and brings the ribbons into tight proximity to the optical waveguides 25, thereby forming the step-like construction consisting of the connected waveguides between the card 10 and the backplane 70. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000236001A

公开(公告)日：2000-08-29

申请号：JP2000005442

申请日：2000-01-14

Applicant: IBM

Inventor： JOSEPH A BENENATTI ,  WILLIAM T CHEN ,  LISA A FANTI ,  WAYNE JOHN HOWEL ,  KNICKERBOCKER JOHN U

IPC: H01L21/56 ,  H01L21/60 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To reduce thermo-kinetic fatigue to a minimum in a flip-chip package. SOLUTION: An interposer 400 used for mounting a flip-chip is made of an organic polymer which includes an aperture 33, having a conductive plug 433 and selected in a such way that an optimum length between a substrate and a chip with a coefficient of thermal expansion in matching with the extremum of a thermal cycle temperate of the module component can be obtained. The conductive plug 433 is made of a high-temperature solder 40, provided in an inside of the aperture 33 and a low-temperature solder 45 provided to the outer side of the high-temperature solder 40. Then, a low- temperature solder 45 is subjected to reflow, while the high-temperature solder becomes solid.

公开(公告)号：JP2007294954A

公开(公告)日：2007-11-08

申请号：JP2007104611

申请日：2007-04-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： STEVEN ALAN CORDES ,  SPEIDELL JAMES L ,  GRUBER PETER ALFRED ,  KNICKERBOCKER JOHN U

IPC: H05K3/34 ,  H05K3/10

CPC classification number: H05K3/3484 ,  B23K3/0607 ,  B23K2201/42 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09472 ,  H05K2203/0126 ,  H05K2203/043 ,  H05K2203/0568

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for feeding conductive bonding material into a plurality of cavities in a circuit support substrate.
SOLUTION: The system, the method and a device for feeding the conductive bonding material into the plurality of cavities in the circuit support substrate are disclosed. The method includes a step for setting up a filling head in a state that it contacts the circuit support substrate substantially. The circuit support substrate includes at least one cavity. While the filling head contacts the circuit support substrate substantially, straight-line motion or rotational movement is imparted to at least one of the circuit support substrate and the filling head. The conductive bonding material is extruded toward the circuit support substrate from the filling head. At the same time at least one cavity comes very close to the filling head, the conductive bonding material is fed into at least the one cavity.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于将导电接合材料馈送到电路支撑衬底中的多个空腔中的系统和方法。 公开了用于将导电接合材料馈送到电路支撑衬底中的多个空腔中的系统，方法和装置。 该方法包括基本上与电路支撑基板接触的状态下设置充填头的步骤。 电路支撑基板包括至少一个空腔。 当填充头基本上接触电路支撑衬底时，直线运动或旋转运动被赋予电路支撑衬底和填充头中的至少一个。 导电接合材料从填充头朝向电路支撑基板挤出。 同时，至少一个空腔非常靠近填充头，导电粘合材料被送入至少一个空腔。 版权所有（C）2008，JPO＆INPIT