公开(公告)号：EP2111637A4

公开(公告)日：2012-08-08

申请号：EP08728172

申请日：2008-01-24

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/768

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

公开(公告)号：EP2433303A4

公开(公告)日：2014-09-17

申请号：EP09845033

申请日：2009-05-22

Applicant: IBM

Inventor： FILIPPI RONALD ,  STANDAERT THEODORUS E ,  GRUNOW STEPHAN ,  SANKARAN SUJATHA ,  CHANDA KAUSHIK ,  GAMBINO JEFFREY P ,  SIMON ANDREW H ,  HU CHAO-KUN ,  BONILLA GRISELDA

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2008091985A3

公开(公告)日：2008-10-02

申请号：PCT/US2008051870

申请日：2008-01-24

Applicant: IBM ,  BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

Abstract: A dielectric cap (100) and related methods are disclosed. In one embodiment, the dielectric cap (100) includes a dielectric material (108) having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap (100) exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

Abstract translation: 公开了一种电介质帽（100）和相关方法。 在一个实施例中，电介质帽（100）包括具有光学带隙（例如，大于约3.0电子伏特）的介电材料（108）以在固化处理期间基本上阻挡紫外辐射，并且包括具有电子供体的氮， 双键电子。 电介质帽（100）表现出高模量，并且在例如铜低k线后端（BEOL）纳米电子器件的ULK UV固化处理下稳定，导致更少的膜和器件开裂以及更高的可靠性 。

公开(公告)号：WO2012134801A3

公开(公告)日：2013-01-03

申请号：PCT/US2012028847

申请日：2012-03-13

Applicant: IBM ,  FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

Inventor： FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias (122, 132). The stacking of vias (122, 132) leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner (124) and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Abstract translation: 具有堆叠通孔（122,132）的线（BEOL）熔丝结构的后端。 通孔（122,132）的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬垫（124）和种子层的弱点导致较高的电迁移（EM）故障概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔断器编程之后损坏区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：WO2012058011A3

公开(公告)日：2012-06-14

申请号：PCT/US2011056119

申请日：2011-10-13

Applicant: IBM ,  FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

Inventor： FILIPPI RONALD ,  WANG PING-CHUAN ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  EDWARDS ROBERT D ,  SIMON ANDREW H

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure including a dielectric layer (202) having a conductive feature (204) embedded therein, the conductive feature (204) having a first top surface (208) that is substantially coplanar with a second top surface (206) of the dielectric layer (202); a metal cap layer (212) located directly on the first top surface (208), wherein the metal cap layer (212) does not substantially extend onto the second top surface (206); a first dielectric cap layer (21 0A) located directly on the second top surface (206), wherein the first dielectric cap layer (21 0A) does not substantially extend onto the first top surface (208) and the first dielectric cap layer (210A) is thicker than the metal cap layer (212); and a second dielectric cap layer (220) on the metal cap layer (212) and the first dielectric cap layer (210A). A method of forming the interconnect structure is also provided.

Abstract translation: 一种改进的互连结构，包括具有嵌入其中的导电部件（204）的电介质层（202），所述导电部件（204）具有与电介质的第二顶表面（206）基本共面的第一顶表面 层（202）; 直接位于所述第一顶面（208）上的金属盖层（212），其中所述金属盖层（212）基本上不延伸到所述第二顶面（206）上; 直接位于第二顶表面（206）上的第一电介质盖层（210A），其中第一电介质盖层（210A）基本上不延伸到第一顶表面（208）上并且第一电介质盖层（210A） ）比金属盖层（212）厚; 和在金属盖层（212）和第一电介质盖层（210A）上的第二电介质盖层（220）。 还提供了形成互连结构的方法。

公开(公告)号：DE112013000362T5

公开(公告)日：2014-10-02

申请号：DE112013000362

申请日：2013-01-10

Applicant: IBM

Inventor： BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H ,  BAO JUNJING ,  FILIPPI RONALD G

IPC: H01L21/82 ,  H01L23/62

Abstract: Es wird eine BEOL-E-Sicherung offenbart, die zuverlässig im Durchkontakt durchbrennt und selbst in den BEOL-Schichten mit engsten Abständen gebildet werden kann. Die BEOL-E-Sicherung kann mit einem Line-First-Dual-Damascene-Prozess gebildet werden, um einen sublithografischen Durchkontakt zu ergeben, der das programmierbare Element der E-Sicherung ist. Der sublithografische Durchkontakt kann durch Standard-Lithografie strukturiert werden, und der Querschnitt des Durchkontakts kann dem Sollprogrammierstrom entsprechend abgestimmt werden.

公开(公告)号：GB2523948A

公开(公告)日：2015-09-09

申请号：GB201511991

申请日：2013-12-09

Applicant: IBM

Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  FILIPPI RONALD G ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  CHOI SAMUEL S

IPC: H01L23/532 ,  H01L21/768

Abstract: A graphene and metal interconnect structure and methods of making the same. A multiple layer graphene structure may be grown using a graphene catalyst. The graphene forms an electrical connection 30 between two or more vias (16,36) or components 20, or a combination of vias and components. A via includes a fill metal, with at least a portion of the fill metal 36 being surrounded by a barrier metal 38. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300°C - 400°C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.

公开(公告)号：GB2512009A

公开(公告)日：2014-09-17

申请号：GB201412533

申请日：2013-01-10

Applicant: IBM

Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  FILIPPI RONALD G ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H

IPC: H01L21/768 ,  H01L23/525

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：GB2512009B

公开(公告)日：2015-02-25

申请号：GB201412533

申请日：2013-01-10

Applicant: IBM

Inventor： BAO JUNJING ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  CHOI SAMUEL S ,  FILIPPI RONALD G ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  MOY DAN ,  SIMON ANDREW H

IPC: H01L21/768 ,  H01L23/525

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：SG159452A1

公开(公告)日：2010-03-30

申请号：SG2009051111

申请日：2009-07-30

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： BONILLA GRISELDA ,  TIEN CHENG ,  CLEVENGER LAWRENCE A ,  GRUNOW STEPHAN ,  CHAO-KUN HU ,  QUON ROGER A ,  ZHIGUO SUN ,  WEI-TSUI TSENG ,  YIHENG XU ,  YUN WANG ,  SANG OH HYEOK

Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiWCXNYHZ disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiWCXNYHZ disposed upon the second capping layer, wherein a + b + c + d = 1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w + x + y + z = 1.0 and w, x, y, and z are each greater than 0 and less than 1.