公开(公告)号：EP2111637A4

公开(公告)日：2012-08-08

申请号：EP08728172

申请日：2008-01-24

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/768

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP2377148A4

公开(公告)日：2016-03-16

申请号：EP09836605

申请日：2009-11-19

Applicant: IBM ,  FREESCALE SEMICONDUCTOR INC

Inventor： RAMACHANDRAN RAVIKUMAR ,  YAN HONGWEN ,  MOUMEN NAIM ,  SCHAEFFER JAMES KENYON ,  KRISHNAN SIDDARTH A ,  WONG KEITH KWONG HON ,  KWON UNOH ,  BELYANSKY MICHAEL P ,  WISE RICHARD

IPC: H01L21/3205 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823857

公开(公告)号：EP1864319A4

公开(公告)日：2009-11-18

申请号：EP06748845

申请日：2006-03-29

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.

公开(公告)号：JP2004363595A

公开(公告)日：2004-12-24

申请号：JP2004159279

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELYANSKY MICHAEL P ,  DIVAKARUNI RAMA ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  SETTLEMYER JR KENNETH T ,  SHAFER PADRAIC C

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76229

Abstract: PROBLEM TO BE SOLVED: To provide a method for filling up a separation trench in a silicon integrated circuit having at least one p-n junction or a phase boundary of different materials before forming a separation structure.
SOLUTION: This method relates to filling of the separation trench and a capacitor trench including a perpendicular field-effect transistor (FET) having aspect ratios up to a maximum of 60 (or p-n junction at an arbitrary front level or the phase boundary of the different materials) obtained through a process. The process comprises a step of coating a spin-on material based on silazane with low molecular weight, a step of performing prebake of the coated material at temperature less than about 450°C within oxygen atmosphere, a step of converting the stress of the material by heating within H
2 O atmosphere at intermediate temperature in the range from 450°C-800°C, a step of obtaining a material stable up to a maximum of 1000°C, which has compressive stress which can be adjusted by changing process parameters resulting from heating again within O
2 atmosphere at high temperature, and which has durability sufficiently resisting to CMP having an etching rate comparable to that of oxide dielectrics formed using the high-density plasma (HDP) technique.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2005333143A

公开(公告)日：2005-12-02

申请号：JP2005147449

申请日：2005-05-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELYANSKY MICHAEL P ,  LIU JOYCE C ,  WANN HSING JEN ,  RICHARD STEPHAN WEISS

IPC: H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: PROBLEM TO BE SOLVED: To provide improved technology for forming high speed logical gate of a semiconductor device.
SOLUTION: An FET (field effect transistor) has: a gate disposed between a source and a drain; a gate dielectric layer disposed under the gate; and spacers disposed on the sides of the gate. The gate dielectric layer is made of a conventional oxide, and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) can be made smaller than 3.85, and can be made larger than 3.85 (approximately same as that of the oxide) and smaller than 7.0 (approximately same as that of nitride). The spacer consists preferably of a material which can be etched selectively in relation to the gate dielectric layer. The spacer can have porosity, and a thin layer which prevents moisture absorption is deposited on a surface of the porous spacer. The spacer can be made of a material which is chosen from the group consisting of Black Diamond, Coral, TERA and a Blok type material. A hole is formed into the material of the spacer by exposing the spacer to oxygen plasma.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于形成半导体器件的高速逻辑门的改进技术。 解决方案：FET（场效应晶体管）具有：设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 以及设置在门的侧面上的间隔物。 栅极电介质层由常规氧化物制成，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，并且可以大于3.85（大致与氧化物相同）且小于7.0（与氮化物大致相同）。 间隔件优选地由可以相对于栅极介电层选择性蚀刻的材料构成。 间隔物可以具有多孔性，并且防止吸湿的薄层沉积在多孔隔离物的表面上。 间隔物可以由选自黑钻石，珊瑚，TERA和Blok型材料的材料制成。 通过将间隔物暴露于氧等离子体中，在隔离物的材料中形成孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2005050701A8

公开(公告)日：2005-11-03

申请号：PCT/US2004037434

申请日：2004-11-09

Applicant: IBM ,  DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L21/8238 ,  H01L31/119 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L31/113

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract translation: 一种制造半导体器件结构的方法，包括：提供衬底（1），在所述衬底（1）上提供电极（6），在所述电极（6）中形成凹部（12），所述凹部具有开口， 在凹部内设置小晶粒半导体材料（17），在凹部内覆盖开口以容纳小晶粒半导体材料，然后对所得结构进行退火。

公开(公告)号：WO2006107669A3

公开(公告)日：2009-04-09

申请号：PCT/US2006011391

申请日：2006-03-29

Applicant: IBM ,  BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material (14) on at least a surface of a substrate (12), said first portion (18) having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified (20) such that the first state of mechanical strain is not substantiaUydtered,\vhile increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times (20, 2OA, 20B) to obtain a preselected and desired thickness for the stressor.

Abstract translation: 提供了一种通过改变这种压力源的内部结构来提高非晶薄膜应力的应力水平的方法。 该方法包括首先在衬底（12）的至少一个表面上形成非晶膜应力材料（14）的第一部分，所述第一部分（18）具有限定第一应力值的第一机械应变状态。 在成形步骤之后，无定形薄膜应力材料的第一部分被致密化（20），使得机械应变的第一状态没有被证实，即增加第一应力值。 在一些实施例中，形成和致密化的步骤重复任意次数（20,20A，20B），以获得应力源的预选和期望的厚度。

公开(公告)号：WO2008091985A3

公开(公告)日：2008-10-02

申请号：PCT/US2008051870

申请日：2008-01-24

Applicant: IBM ,  BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

Inventor： BELYANSKY MICHAEL P ,  BONILLA GRISELDA ,  LIU XIAO HU ,  NGUYEN SON VAN ,  SHAW THOMAS M ,  SHOBHA HOSADURGA K ,  YANG DAEWON

IPC: H01L23/12

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

Abstract: A dielectric cap (100) and related methods are disclosed. In one embodiment, the dielectric cap (100) includes a dielectric material (108) having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap (100) exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

Abstract translation: 公开了一种电介质帽（100）和相关方法。 在一个实施例中，电介质帽（100）包括具有光学带隙（例如，大于约3.0电子伏特）的介电材料（108）以在固化处理期间基本上阻挡紫外辐射，并且包括具有电子供体的氮， 双键电子。 电介质帽（100）表现出高模量，并且在例如铜低k线后端（BEOL）纳米电子器件的ULK UV固化处理下稳定，导致更少的膜和器件开裂以及更高的可靠性 。

公开(公告)号：SG140556A1

公开(公告)日：2008-03-28

申请号：SG2007060536

申请日：2007-08-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG

Inventor： WAY TEH YOUNG ,  WIDODO JOHNNY ,  BELYANSKY MICHAEL P ,  EUN PARK JAE

Abstract: INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer on the wafer, protecting a portion of the stress formation layer, and irradiating the wafer for modification of a stress value of an unprotected portion of the stress formation layer.