Semiconductor structure with improved bonding interface on carbon-based material, method for forming the same, and electronic device
    5.
    发明专利
    Semiconductor structure with improved bonding interface on carbon-based material, method for forming the same, and electronic device 审中-公开
    具有改进的基于碳的材料的接合界面的半导体结构,其形成方法和电子器件

    公开(公告)号:JP2011211175A

    公开(公告)日:2011-10-20

    申请号:JP2011044902

    申请日:2011-03-02

    CPC classification number: H01L29/1606 H01L29/7781 H01L29/78 H01L29/7831

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and electronic device, formed in high density, and having smaller structural dimensions and a more exact shape.SOLUTION: Semiconductor structures and electronic devices include at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material.

    Abstract translation: 要解决的问题:提供一种形成为高密度且具有较小结构尺寸和更精确形状的半导体结构和电子器件。解决方案:半导体结构和电子器件包括至少一层界面介电材料,位于 碳基材料的上表面。 所述至少一层界面介电材料具有与碳基材料相同的短程结晶结合结构,通常是六边形,因此至少一层界面介电材料不会改变 碳基材料的电子结构。 具有与碳基材料相同的短程结晶结合结构的至少一层界面介电材料的存在改善了碳基材料和任何覆盖材料层(包括介电材料)之间的界面结合, 导电材料或介电材料和导电材料的组合。 改进的界面结合又有助于形成包括碳基材料的装置。

    BPSG REFLOW AND METHOD FOR SUPPRESSING PATTERN DISTORTION RELATED TO INTEGRATED CIRCUIT CHIP FORMED BY IT

    公开(公告)号:JPH10135326A

    公开(公告)日:1998-05-22

    申请号:JP27283597

    申请日:1997-10-06

    Applicant: IBM SIEMENS AG

    Abstract: PROBLEM TO BE SOLVED: To increase the densities of borophosphate-silicate glass and an oxide existing on the glass before forming a pattern, by exposing the glass and undoped oxide to a high temperature before a line patterning step, a contact etching step, and an ion implanting step. SOLUTION: After a dielectric layer of borophosphate-silicate glass having fluidity is stuck to the surface of a substrate, another dielectric layer of a material having no fluidity is stuck to the surface of the glass layer. Then, contact etching and a high dose of ion implantation are performed so that an undoped oxide composed of SiO2 existing on the dielectric layer having no fluidity can be exposed to a junction activating annealing temperature, namely, a high annealing temperature of about 800 deg.C to 1,100 deg.C. After the ion implantation, contacts and lines are metallized by again exposing the contacts and lines to a high annealing temperature. Therefore, the densities of the borophosphate-silicate glass and SiO2 existing on the glass can be increased before forming a pattern.

    MANUFACTURE OF STACK CAPACITOR
    10.
    发明专利

    公开(公告)号:JPH10163453A

    公开(公告)日:1998-06-19

    申请号:JP28493997

    申请日:1997-10-17

    Abstract: PROBLEM TO BE SOLVED: To provide a simple damassine manufacturing method for manufacture of a stack capacitor of high aspect surface area suitable for a gigabit DRAM device. SOLUTION: The accumulative charge of a capacitor increases by increasing the accumulative node region. As stack capacitor of high aspect surface area ratio can be manufactured without increasing the maximum cell dimension. The accumulation node is formed by the borophossilicate glass (block 1) in low doped or high doped concentration which is stuck in accurate nanometer dimension by one process stage, and either the doped layer or the nondoped layer is etched (block 3) to have high etching speed. This etching manufactures (block 4) finger-shape shaped protrusions within the nodes, and these protrusion give larger surface region, using a very simplified method where processing stages are limited.

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