公开(公告)号：WO2004043850A3

公开(公告)日：2005-03-24

申请号：PCT/GB0304829

申请日：2003-11-07

Applicant: IBM ,  IBM UK

Inventor： POGGE BERNHARD ,  DESPONT MICHEL ,  DRECHSLER UTE ,  PRASAD CHANDRIKA ,  VETTIGER PETER ,  YU ROY

IPC: B81C3/00 ,  H01L21/768

CPC classification number: B81C1/00238 ,  B81B2203/0307 ,  H01L21/76898 ,  H01L2224/16225

Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Abstract translation: 垂直整合的结构包括微机电系统（MEMS）和用于向MEMS输送信号的芯片。 MEMS具有一个具有穿过其中的导体的锚定部分，通过该锚固部分连接到基底。 该芯片沿着垂直于衬底表面的方向附接到MEMS衬底，从而形成从芯片到MEMS的导电路径。 可以通过将导体接合到形成在芯片上的C4金属焊盘，或者通过将导体粘合到芯片上的金属螺柱来附接芯片。 MEMS基板可以在连接到芯片之前变薄，或者可以从MEMS的下侧移除。 使用临时载体板来促进MEMS的处理和与芯片的对准。

公开(公告)号：EP1668685A4

公开(公告)日：2012-02-29

申请号：EP04756585

申请日：2004-06-29

Applicant: IBM

Inventor： POGGE BERNHARD H ,  PRASAD CHANDRIKA ,  YU ROY

IPC: H01L21/44 ,  B23K31/02 ,  H01L21/60 ,  H01L21/68 ,  H01L23/00 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83365 ,  H01L2224/83907 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599

公开(公告)号：EP1470583A4

公开(公告)日：2005-08-03

申请号：EP02789958

申请日：2002-11-26

Applicant: IBM

Inventor： POGGE BERNHARD H ,  YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate (1). A metallized feature (2) is formed in the top surface of a substrate, and a handling plate (35) is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via (20). The substrate may comprise a chip (44) having a device (30), e.g. a PE chip. The plate may be a wafer (65) attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices (30,60) fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：DE3580314D1

公开(公告)日：1990-12-06

申请号：DE3580314

申请日：1985-06-24

Applicant: IBM

Inventor： PRASAD CHANDRIKA ,  SZEWCZYK ANDREW FRANCIS

IPC: H01L23/50 ,  B23K35/30 ,  H01L21/60 ,  H01L23/12 ,  H01R43/02 ,  H05K3/34

Abstract: A process for bonding a current carrying element (10) to a dielectric substrate (12) having a solder wettable pad (14) of a predetermined diameter, wherein an element (16) is provided having a bonding surface with a dimension that is smaller than the pad and a brazing material (20) that includes Ag and Cu and either In and/or Sn. The brazing material exhibits a mushy zone over a predetermined temperature; it is placed between the element and pad and heated to a temperature to cause the material to be mushy while a pressure is applied to the element to compress the material.

公开(公告)号：AU2002352993A1

公开(公告)日：2003-07-09

申请号：AU2002352993

申请日：2002-11-26

Applicant: IBM

Inventor： YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR ,  POGGE BERNHARD H

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/8234

Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：DE3266912D1

公开(公告)日：1985-11-21

申请号：DE3266912

申请日：1982-06-15

Applicant: IBM

Inventor： FLEMING REBECCA POWERS ,  LAWNHORNE JR ,  MELE JOHN JOSEPH ,  PRASAD CHANDRIKA

IPC: C23C18/34 ,  C23C10/28 ,  C23C18/16 ,  H01L21/288 ,  H05K3/38 ,  C23C18/32 ,  C03C17/10

Abstract: A method of providing a stress-free metal layer by electroless plating techniques, including the steps of (1) providing a substrate that includes some glass material in at least the surface areas to receive a metal layer, (2) depositing a layer of metal-boron by electroless plating techniques, and (3) heating the resultant metal-boron layer in a non-reacting and/or H2 environment at a temperature of at least 750 DEG C. for a time sufficient to diffuse the boron to the glass material in the substrate.

公开(公告)号：AU2003301975A1

公开(公告)日：2004-06-03

申请号：AU2003301975

申请日：2003-11-07

Applicant: IBM

Inventor： POGGE BERNHARD ,  DESPONT MICHEL ,  DRECHSLER UTE ,  PRASAD CHANDRIKA ,  VETTIGER PETER ,  YU ROY

IPC: B81C3/00 ,  H01L21/768

Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

公开(公告)号：DE3366861D1

公开(公告)日：1986-11-20

申请号：DE3366861

申请日：1983-11-08

Applicant: IBM

Inventor： MILLER WILLIAM ROBERT ,  PRASAD CHANDRIKA

IPC: H01L23/12 ,  B23K35/00 ,  B23K35/30 ,  H01L21/48 ,  H01L23/50 ,  B23K1/00