公开(公告)号：DE69632768D1

公开(公告)日：2004-07-29

申请号：DE69632768

申请日：1996-09-04

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES E ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L21/763 ,  H01L21/334

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si3N4) in shallow trench isolation (STI) structures as an O2-barrier film. The crystalline Si3N4 lowers the density of electron traps as compared with as-deposited, amorphous Si3N4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si3N4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si3N4 film is deposited at temperatures of 720 DEG C to 780 DEG C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050 DEG C to 1100 DEG C for 60 seconds.

公开(公告)号：DE69632768T2

公开(公告)日：2005-07-07

申请号：DE69632768

申请日：1996-09-04

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES E ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L21/763 ,  H01L21/334

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si3N4) in shallow trench isolation (STI) structures as an O2-barrier film. The crystalline Si3N4 lowers the density of electron traps as compared with as-deposited, amorphous Si3N4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si3N4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si3N4 film is deposited at temperatures of 720 DEG C to 780 DEG C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050 DEG C to 1100 DEG C for 60 seconds.

公开(公告)号：JP2000223684A

公开(公告)日：2000-08-11

申请号：JP2000017676

申请日：2000-01-26

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a substrate contact in a substrate with a silicon-on-insulator region. SOLUTION: A shallow isolation trench is formed in a silicon-on-insulator. The shallow isolation trench is filled. A photoresist is glued onto a substrate. A contact trench is formed in the substrate through the filled, shallow isolation trench, the silicon-on-insulator, and a silicon substrate 3 at the lower side of the silicon-on-insulator. The contact trench is filled, a material 21 for filling the contact trench forms a contact to the silicon substrate 3, and grounds the substrate 3, thus solving the problem of the accumulation of static charge in the substrate 3.

公开(公告)号：JP2005340816A

公开(公告)日：2005-12-08

申请号：JP2005147746

申请日：2005-05-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN KEVIN K ,  MILLER ROBER J ,  JONES ERIN C ,  AJMERA ATUL

IPC: H01L21/225 ,  C30B1/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/331 ,  H01L21/336 ,  H01L21/36 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2252 ,  H01L21/31695 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a MOSFET device having a polycrystalline SiGe junction.
SOLUTION: Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers produce a SiGe junction. The deposited layers are doped, and then the dopants are outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junction.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有多晶SiGe结的MOSFET器件的结构和制造方法。 解决方案：Ge选择性地生长在Si上，而Si选择性地生长在Ge上。 Ge和Si层的交替沉积产生SiGe结。 沉积的层被掺杂，然后掺杂物向外扩散到器件本体中。 多晶Ge和Si层之间的薄多孔氧化物层增强了SiGe结的各向同性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000208746A

公开(公告)日：2000-07-28

申请号：JP37300499

申请日：1999-12-28

Applicant: IBM

Inventor： AJMERA ATUL ,  DEVENDORA K SADANA ,  DOMINIK J SHEPISU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an SOI layer with a pattern wherein no transition region containing many defects is formed. SOLUTION: A flat silicon-on-insulator(SOI) substrate having no transition defect containing an SOI region with a pattern and a bulk area is formed. This method contains a stage of removing transition defects by forming a self- matched trench 30 adjacent to the SOI area 22 between the SOI region and the bulk region 24.

公开(公告)号：JPH10214889A

公开(公告)日：1998-08-11

申请号：JP2253198

申请日：1998-01-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES F ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To contain a trapping center with a lower density than before conversion, by depositing an Si3 N4 covering with a specific thickness in an STI structure by the low-pressure chemical vapor deposition method, performing speedy heat annealing under specific conditions immediately after depositing the covering, and converting Si3 N4 from amorphous to a crystal material. SOLUTION: After a shallow trench is etched, a thin thermal oxide with a thickness of approximately 10nm is grown to eliminate an etching damage. Then, an Si3 N4 covering with a thickness of 5-10nm is deposited on the upper surface of an oxide layer in amorphous state at a temperature of 720-780 deg.C in a shallow trench isolation structure(STI). Then, immediately after the covering is deposited, a high-speed heat annealing is executed nearly for 60 seconds at 1,050-1,150 deg.C in pure nitrogen or ammonium and the Si3 N4 covering is converted from the amorphous state to the crystal material state of a low- temperature-hexagonal (d) Si3 N4 phase.

公开(公告)号：GB2346260A

公开(公告)日：2000-08-02

申请号：GB0001370

申请日：2000-01-24

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: A method of forming a contact to the substrate 3 of a silicon-on-insulator semiconductor device comprises forming an isolation trench (11, Fig 2) in the silicon layer 7, filling the trench with TEOS and forming a contact trench through the isolation trench such that the contact trench makes contact with the underlying substrate 3. The contact trench is filled with polysilicon 21 or tungsten and may be ring shaped to form a guard ring. The contact trench may be used to ground the substrate.

公开(公告)号：GB2346260B

公开(公告)日：2004-01-28

申请号：GB0001370

申请日：2000-01-24

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

公开(公告)号：SG135103A1

公开(公告)日：2007-09-28

申请号：SG2007007990

申请日：2007-02-07

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHEN XIANGDONG ,  BAIOCCO CHRISTOPHER V ,  AJMERA ATUL ,  TEH YOUNG WAY ,  GAO WENZHI

Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer (50) composed of a first oxide (130) and first nitride (40) layer is applied to a gate electrode (10) on a substrate (20), and a second spacer (60) composed of a second oxide (70) and a second nitride (80) layer is applied. Deep implanting of source and drain in the substrate (20) occurs, and removal of the second nitride (80), second oxide (70), and first nitride layers (40).