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    A LOW-K PRE-METAL DIELECTRIC SEMICONDUCTOR STRUCTURE
    1.
    发明申请
    A LOW-K PRE-METAL DIELECTRIC SEMICONDUCTOR STRUCTURE 审中-公开
    低K预金属介电半导体结构

    公开(公告)号：WO03019619A3

    公开(公告)日：2003-10-16

    申请号：PCT/US0225507

    申请日：2002-08-08

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： CONTI RICHARD A ,  EDELSTEIN DANIEL ,  LEE GILL YONG

    IPC: H01L21/768 ,  C23C16/40 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522 ,  H01L21/02

    CPC classification number: H01L21/31604 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A low-k pre-metal dielectric (PMD) structure on a semiconductor wafer and a method for making the PMD structure is described. The PMD structure includes a low-k dielectric film (170) that has good gap-filling characteristics, particularly where the gap (160) formed between features (130), such as gate stacks, has an aspect ratio greater than about 3. The method for forming the PMD structure uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precursor (260) such as TMCTS or OMCTS, an ozone-containing gas (270), and a source of dopants (280) for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film (170). Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combination thereof.

    Abstract translation: 描述半导体晶片上的低k金属前介电（PMD）结构和制造PMD结构的方法。 PMD结构包括具有良好间隙填充特性的低k介电膜（170），特别是在特征（130）之间形成的间隙（160）（例如栅极堆叠）具有大于约3的纵横比时。 用于形成PMD结构的方法使用包括诸如TMCTS或OMCTS的含碳有机金属前体（260），含臭氧气体（270）和用于吸杂的掺杂剂源（280）的热亚低气压CVD工艺 碱性元素并降低电介质的回流温度，同时获得电介质膜（170）的期望的低k和间隙填充性能。 磷是吸收碱金属元素如钠的优选掺杂剂。 用于降低回流温度的附加掺杂剂包括但不限于硼，锗，砷，氟或其组合。

    A low-k pre-metal dielectric semiconductor structure
    2.
    发明专利
    A low-k pre-metal dielectric semiconductor structure 未知

    公开(公告)号：AU2002323112A1

    公开(公告)日：2003-03-10

    申请号：AU2002323112

    申请日：2002-08-08

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： EDELSTEIN DANIEL ,  LEE GILL YONG ,  CONTI RICHARD A

    IPC: H01L21/768 ,  C23C16/40 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522 ,  H01L21/02

    Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

    COMPLIANT PASSIVATED EDGE SEAL FOR LOW-K INTERCONNECT STRUCTURES
    5.
    发明申请
    COMPLIANT PASSIVATED EDGE SEAL FOR LOW-K INTERCONNECT STRUCTURES 审中-公开
    适用于低K互连结构的合适封闭边缘密封

    公开(公告)号：WO2005067598A3

    公开(公告)日：2006-11-23

    申请号：PCT/US2005000289

    申请日：2005-01-06

    Applicant: IBM ,  EDELSTEIN DANIEL ,  NICHOLSON LEE M

    Inventor： EDELSTEIN DANIEL ,  NICHOLSON LEE M

    IPC: H01L23/34 ,  H01L23/053 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31

    CPC classification number: H01L23/3135 ,  H01L23/3121 ,  H01L23/3178 ,  H01L23/3185 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2224/29099 ,  H01L2924/00

    Abstract: A structure for a chip (11) or chip package is disclosed, with final passivation (17) and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads (14) therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to Si0 2 . The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

    Abstract translation: 公开了一种用于芯片（11）或芯片封装的结构，其中最终钝化（17）和终端冶金机械地去耦合但电耦合到多层片上互连。 该去耦允许芯片在最终钝化区域中经受包装应力，其中去耦区域和柔性引线（14）的应变消除，使得片上互连电平不会感受到这些外部封装或其它应力。 这种结构对于由Cu和低k电介质组成的片上互连是特别优选的，后者相对于Si 2 O 2具有较差的机械性能。 去耦区延伸在晶片上的所有芯片上。 它还可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围的这种机械去耦的芯片切割和保持。

    Conductive structure for narrow interconnect openings
    9.
    发明专利
    Conductive structure for narrow interconnect openings 未知

    公开(公告)号：GB2485689A

    公开(公告)日：2012-05-23

    申请号：GB201200519

    申请日：2010-08-25

    Applicant: IBM

    Inventor： ROSSNAGEL STEPHEN ,  YANG CHIH-CHAO ,  EDELSTEIN DANIEL ,  NOGAMI TAKESHI

    IPC: H01L21/768

    Abstract: An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material (24) including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer (30), a grain growth promotion layer (32), an agglomerated plating seed layer (34'), an optional second plating seed layer a conductive structure (38). The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.

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