公开(公告)号：JP2000315782A

公开(公告)日：2000-11-14

申请号：JP2000123911

申请日：2000-04-25

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RUPP THOMAS S ,  DOBUZINSKY DAVID M ,  LU ZHIJIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a stable contact resistance and also has an aligned maximum allowable contact region adapted to reduced fundamental dimensions. SOLUTION: A borderless contact 11 of giga-scale fundamental dimensions is spread in a direction perpendicular to word lines 14 (in a direction parallel to bit lines 16). Formation of a borderless contact structure of another square into a rectangular structure causes reduction of a step positional deviation, thus decreasing a contact resistance and keeping its uniformity. A maximum allowable contact region can be obtained even with a positionally shifted arrangement.

公开(公告)号：WO0198836A3

公开(公告)日：2002-04-18

申请号：PCT/US0119814

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LU ZHIJIAN ,  THOMAS ALAN ,  GUTMANN ALOIS ,  CHEN KUANG JUNG ,  LAWSON MARGARET

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/09

CPC classification number: H01L21/0274 ,  G03F7/2022 ,  G03F7/2037 ,  G03F7/2039 ,  Y10S430/168

Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50 % of the dose-to-clear for a non-patterned exposure.

Abstract translation: 在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致光致抗蚀剂材料的不希望的部件的高密度，残留在 半导体衬底（主体）。 曝光和显影光致抗蚀剂材料的方法导致这些斑点缺陷的发生率降低，除了通常使用的图案光曝光之外，还引入低等级的均匀泛光曝光，随后进行标准开发。 对于非图案化曝光，洪水暴露在5至50％的剂量清除范围内。

公开(公告)号：WO0199161A2

公开(公告)日：2001-12-27

申请号：PCT/US0119815

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LU ZHIJIAN ,  THOMAS ALAN ,  GUTMANN ALOIS ,  CHEN KUANG JUNG ,  LAWSON MARGARET

IPC: G03F7/30 ,  H01L21/00

CPC classification number: G03F7/3021

Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable remnants (denoted as Blob Defects) of various components of photoresist material remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of using a Puddle Development technique to develop the photoresist material, and subsequently exposing the semiconductor wafer to at least one Puddle Rinse cycle which uses water.

Abstract translation: 在可用的深紫外（DUV）敏感光刻胶的曝光和显影中，已经观察到遵循现有技术的标准曝光和显影方法导致残留的光致抗蚀剂材料的各种组分的不希望的残留物（表示为Blob缺陷）的高密度 在半导体基板（主体）上。 曝光和显影光致抗蚀剂材料的方法导致这些Blob缺陷的发生率降低，包括使用水坑开发技术开发光致抗蚀剂材料，随后将半导体晶片暴露于使用水的至少一个水坑冲洗循环。

公开(公告)号：WO0223598A3

公开(公告)日：2002-06-13

申请号：PCT/US0142148

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LU ZHIJIAN ,  MOREAU WAYNE ,  CHEN KUANG JUNG ,  MACK GEORGE

IPC: C11D1/14 ,  C11D11/00 ,  G03F7/30 ,  G03F7/32 ,  G03F7/40

CPC classification number: C11D11/0047 ,  C11D1/146 ,  G03F7/3021 ,  G03F7/32 ,  G03F7/322 ,  G03F7/40

Abstract: Post-development defects in the manufacture of semiconductor devices through the use of surfactants, suchas ammonium lauryl sulfate, incorporated in the rinse water or the developer for the resist. The surfactants effectively remove resist defects in or around the resist pattern without attacking the resist itself.

Abstract translation: 通过使用表面活性剂制造半导体器件的后期缺陷，例如掺入漂洗水中的月桂基硫酸铵或用于抗蚀剂的显影剂。 表面活性剂有效去除抗蚀剂图案内或周围的抗蚀剂缺陷，而不会侵蚀抗蚀剂本身。

公开(公告)号：DE60142833D1

公开(公告)日：2010-09-30

申请号：DE60142833

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LU ZHIJIAN ,  THOMAS ALAN ,  GUTMANN ALOIS ,  CHEN KUANG JUNG ,  LAWSON MARGARET

IPC: G03F7/30

公开(公告)号：JP2000299282A

公开(公告)日：2000-10-24

申请号：JP2000086623

申请日：2000-03-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TOEBBEN DIRK DR ,  LEE GILL YOUNG ,  LU ZHIJIAN

IPC: G03F7/004 ,  G03F7/09 ,  G03F7/11 ,  G03F7/26 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide an ARC(antireflection coating) layer which effects more improved CD(critical dimension) control, so as to lessen a resist layer in reflectivity in a lithographic process. SOLUTION: This reduction method is carried out in a manner, where an antireflection coating layer 130 is deposited on a board 130, and a resist layer 170 is deposited on the ARC layer 130, where the ARC layer 130 is composed of a first section 135 and a second section 140, the first section 135 operates in an absorption mode, and the reflectivity of the second section 140 is so set as to reduce the reflectivity difference between the first section 135 and the resist layer 170.

公开(公告)号：WO0229887A3

公开(公告)日：2003-02-06

申请号：PCT/US0126998

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LU ZHIJIAN ,  NING XIAN J ,  YIN XIAOMING

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76813

Abstract: A method for forming a dual damascene structure, employs the steps of forming a dielectric layer (14), patterning a first resist layer (16) on the dielectric layer to form a via pattern (26) and patterning a second resist layer (28) to form a line pattern (38) in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via (40) formed therein which gets deeper during the etching process. The dielectric layer has a trench (42) formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.

Abstract translation: 一种用于形成双镶嵌结构的方法，采用以下步骤：形成电介质层（14），图案化介电层上的第一抗蚀剂层（16）以形成通孔图案（26）并使第二抗蚀剂层（28）构图， 以形成与形成在第一抗蚀剂层上的通孔图案相连的线图案，其中第一抗蚀剂层包括与通孔图案相邻的暴露部分。 蚀刻第一抗蚀剂层，第二抗蚀剂层和电介质层，使得介电层具有在其中形成的通孔（40），其在蚀刻工艺期间变深。 电介质层具有形成在其中的与通孔连通的沟槽（42），其在通过蚀刻工艺消耗第一抗蚀剂层的暴露部分之后变深。

公开(公告)号：DE60007208D1

公开(公告)日：2004-01-29

申请号：DE60007208

申请日：2000-03-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TOEBBEN DIRK ,  LEE YONG GILL ,  LU ZHIJIAN

IPC: G03F7/004 ,  G03F7/09 ,  G03F7/11 ,  G03F7/26 ,  H01L21/027

Abstract: An ARC that reduces the reflectivity in the resist is described. The ARC comprises first and sections. The first section operates in the absorption mode and the second section reduces the difference in the refractive indices between the resist and first ARC section, thereby improving CD control.

公开(公告)号：JP2000031281A

公开(公告)日：2000-01-28

申请号：JP17745099

申请日：1999-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： SCHNABEL RAINER F ,  GAMBINO JEFFREY ,  LU ZHIJIAN

IPC: H01L21/027 ,  H01L21/768 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To reduce layout area in the production process of semiconductor chip by reflecting radiation from a reflective material to a resist layer and increasing irradiation of the resist layer at the time of development. SOLUTION: A metal layer including a conductive or metal line 14 is formed in a dielectric layer 12 and a silicon dioxide layer 16 containing a dielectric material is formed on the metal layer. A transparent resist layer 18 is formed on the layer 16 and a light beam from a radiation source 20 is transmitted through the layers 18, 16 in the direction of arrow A. The radiation light beam is reflected on the metal line 14 and transmitted again through the resist layer 18 at location 28 and the radiation light beam not impinging on the metal line 14 is substantially absorbed by the dielectric layer 12. More specifically, the resist layer 18 is developed while increasing irradiation with radiation light.