公开(公告)号：WO0106542A3

公开(公告)日：2001-07-19

申请号：PCT/DE0002316

申请日：2000-07-17

Applicant: INFINEON TECHNOLOGIES AG ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

Abstract translation: 在衬底（1）上构建双栅MOSFET半导体层结构。 这在半导体沟道层区的相对的端面由第一和在其之间的半导体沟道层区域（4A）被嵌入第二栅电极（10A，10B），以及源极（2A）和漏极区域（2b）中的 （4A）被布置。 在其中一个栅电极（10B）上提供至少一个另外的半导体沟道层区域（6A），其端面同样与源极（2A）和漏极区域（2B）接触。

公开(公告)号：DE59509972D1

公开(公告)日：2002-01-31

申请号：DE59509972

申请日：1995-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AEUGLE THOMAS

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/095

Abstract: PCT No. PCT/DE95/01213 Sec. 371 Date Mar. 7, 1997 Sec. 102(e) Date Mar. 7, 1997 PCT Filed Sep. 6, 1995 PCT Pub. No. WO96/08843 PCT Pub. Date Mar. 21, 1996Integrated circuit structure having an active microwave component and at least one passive component. A high-resistance silicon substrate (11) comprises an active microwave component (16) and at least two metallization planes (12, 14), which are insulated from one another by an insulation layer (13). A passive component surrounded by a grounded line (122) in one of the metallization planes (12) is provided, which comprises a first metal structure (121), which is realized in the first metallization plane (12), and a second metal structure (141), which is realized in the other metallization plane (14). The passive component is designed, in particular, as a capacitor, coil or resonator which comprises a capacitor and a coil.

公开(公告)号：DE19933564C1

公开(公告)日：2001-01-25

申请号：DE19933564

申请日：1999-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L29/78

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

公开(公告)号：DE59814314D1

公开(公告)日：2008-12-11

申请号：DE59814314

申请日：1998-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS ,  ROESNER WOLFGANG ,  RISCH LOTHAR

IPC: H01L29/78 ,  H01L21/336

Abstract: A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

公开(公告)号：DE59804805D1

公开(公告)日：2002-08-22

申请号：DE59804805

申请日：1998-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  UNIV RUHR BOCHUM

Inventor： AEUGLE THOMAS ,  ROESNER WOLFGANG ,  BEHAMMER DAG

IPC: H01L21/336 ,  H01L29/78

Abstract: In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which essentially covers the side walls of the lower source/drain region. A gate dielectric and a gate electrode, whose height is essentially equal to the height of the channel region, are formed on the side walls of the channel region.

公开(公告)号：DE19746900C2

公开(公告)日：2002-02-14

申请号：DE19746900

申请日：1997-10-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS ,  ROESNER WOLFGANG

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/78

Abstract: A first part (S/D1a) of a first source/drain region (S/D1) is disposed on at least one flank of a semiconductor structure (St) and on at least one peripheral region of a surface (OH), bordering the flank, of the semiconductor structure (St). A dimension of the first part (S/D1a) of the first source/drain region (S/D1) perpendicular to the flank is less than an analogous dimension of the semiconductor structure (St) and than the minimum feature size that can be made by the technology used. For the production, a mask that is used to create the semiconductor structure (St) can be reduced in size for the implantation of the first part (S/D1a) of the first source/drain region (S/D1). To make it easier to create a contact (K1) of the first source/drain region (S/D1), a second part (S/D1b) of the first source/drain region (S/D1) can be disposed in an inner region of the surface (OH) of the semiconductor structure (St). A dimension of the second part (S/D1b) of the first source/drain region (S/D1) perpendicular to the surface (OH) of the semiconductor structure (St) is smaller than an analogous dimension of the first part (S/D1a) of the first source/drain region (S/D1).