公开(公告)号：WO03015163A2

公开(公告)日：2003-02-20

申请号：PCT/EP0207313

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG ,  BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249

CPC classification number: H01L21/8249

Abstract: The invention relates to a method for the parallel production of an MOS transistor in an MOS area of a substrate (1) and a bipolar transistor in a bipolar area of said substrate (1). The method comprises the creation of an MOS preconditioning structure in the MOS area, whereby the MOS preconditioning structure contains a region (13) provided for a channel, a gate dielectric (14), a gate electrode layer (15, 19) and a masking layer (21a, 21b, 22) on the gate electrode layer (15, 19). In addition, a bipolar preconditioning structure is created in the bipolar area, said structure comprising a conductive layer (20) and a masking layer (21a, 21b, 22) on the conductive layer (20). To establish a gate electrode and a base connection region, the gate electrode layer (15, 19) and the conductive layer (20) are jointly structured. The invention also relates to the simultaneous creation of isolating spacer layers (30, 31) on lateral walls of the gate electrode layer in the MOS area and on the conductive layer in the bipolar area by the application of a first (30) and second spacer layer (31). The isolating spacer layers define the regions to be doped in the MOS area and isolate a base region and an emitter region in the bipolar area. Finally, the first spacer layer (30) and the second spacer layer (31) are selectively etched in the MOS and bipolar areas.

Abstract translation: 本发明提供了一种在衬底（1）的MOS区中并联制造MOS晶体管的方法以及在衬底（1）的双极区中的双极晶体管的制造方法。 该方法包括在MOS区中生成MOS准备结构，该MOS准备结构包括为沟道设置的区域（13），栅极电介质（14），栅电极层（15,19）和掩模层（21a， 21b，22）设置在栅电极层（15,19）上。 此外，在双极区中产生双极预备结构，双极区包括导电层（20）上的导电层（20）和掩模层（21a，21b，22）。 为了限定栅极电极和基极端子区域，执行栅极电极层（15,19）和导电层（20）的通用结构化。 该方法还包括通过沉积第一（30）和第二间隔层（31）在MOS区栅电极层和双极导电层的侧壁上同时形成绝缘间隔层（30,31）。 在MOS区中使用绝缘间隔层来定义要掺杂的区域，并且在用于隔离基极区和发射极区的双极区中使用绝缘间隔层。 随后，执行MOS区和双极区中的第一间隔层（30）和第二间隔层（31）的选择性蚀刻。

公开(公告)号：DE59606550D1

公开(公告)日：2001-04-12

申请号：DE59606550

申请日：1996-04-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NAEHER ULRICH ,  BERTHOLD ADRIAN ,  SCHEITER THOMAS ,  HIEROLD CHRISTOFER

IPC: G01L9/12 ,  G01L1/14 ,  G01L9/00 ,  G01P15/08 ,  G01P15/125 ,  H01L29/84

公开(公告)号：DE50208719D1

公开(公告)日：2006-12-28

申请号：DE50208719

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249 ,  H01L27/06

Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

公开(公告)号：DE102008000141A1

公开(公告)日：2008-08-07

申请号：DE102008000141

申请日：2008-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BIANCO MICHAEL ,  MAHNKOPF REINHARD

IPC: H01L29/78 ,  H01L21/336

Abstract: A low noise transistor and a method of making a low noise transistor. A noise-reducing agent is introduced into the gate electrode and then moved into the gate dielectric of a transistor.

公开(公告)号：DE10138648A1

公开(公告)日：2003-03-06

申请号：DE10138648

申请日：2001-08-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249 ,  H01L27/06

Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

公开(公告)号：DE102008000141B4

公开(公告)日：2014-02-20

申请号：DE102008000141

申请日：2008-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BIANCO MICHAEL ,  MAHNKOPF REINHARD

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

Abstract: Verfahren zum Ausbilden eines Feldeffekttransistors mit den Schritten: Ausbilden eines Gatestapels über einem Halbleitermaterial, wobei der Gatestapel ein über dem Halbleitermaterial ausgebildetes Gatedielektrikum (52) und eine über dem Gatedielektrikum ausgebildete Gateelektrode (56) beinhaltet; Einbringen eines rauschen-reduzierenden Mittels (90) in die Gateelektrode (56); und Verschieben von zumindest einem Teil des rauschen-reduzierenden Mittels (90) von der Gateelektrode (56) in das Gatedielektrikum (52), wobei der Schritt des Einbringens eine Ionenimplantation aufweist, bei der die Dosis des rauschen-reduzierenden Mittels (90) größer als oder gleich ungefähr 1016 Ionen/cm2ist.

公开(公告)号：DE50202496D1

公开(公告)日：2005-04-21

申请号：DE50202496

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249 ,  H01L27/06

Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.