公开(公告)号：WO2005043623A2

公开(公告)日：2005-05-12

申请号：PCT/EP2004052594

申请日：2004-10-20

Applicant: INFINEON TECHNOLOGIES AG ,  GSCHWANDTNER ALEXANDER ,  HOLZ JUERGEN ,  SCHRENK MICHAEL

Inventor： GSCHWANDTNER ALEXANDER ,  HOLZ JUERGEN ,  SCHRENK MICHAEL

IPC: C23C14/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/511 ,  H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08

CPC classification number: C23C16/45542 ,  C23C16/345 ,  C23C16/45523 ,  C23C16/511 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method that permits the direct application of a dielectric layer to a metallic layer containing copper. According to said method, two process gases (26, 28) are excited by means of respectively different plasma powers for each substrate surface or one of the process gases (26) is excited by means of a plasma and the other process gas (28) is not excited.

Abstract translation: 解释措施，除其他外， 允许电介质层的上的含铜金属的直接应用。 因此，两种处理气体是（26,28），兴奋与每个衬底表面相互不同的等离子体功率或处理气体（26）被激发的等离子和其它工艺气体（28）不被激励。

公开(公告)号：WO2004064160A2

公开(公告)日：2004-07-29

申请号：PCT/EP0314974

申请日：2003-12-31

Applicant: INFINEON TECHNOLOGIES AG ,  BARTH HANS-JOACHIM ,  HOLZ JUERGEN

Inventor： BARTH HANS-JOACHIM ,  HOLZ JUERGEN

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/00

Abstract: The invention relates to a method for producing an integrated circuit arrangement (100) comprising a capacitor (112). A dielectric layer (160) is structured with the aid of a hard mask during a two-stage etching process. The hard mask is subsequently removed if it is an electrically insulating hard mask. If the latter is an electrically conductive hard mask, parts of said mask can remain in the circuit arrangement (100). The integrated circuit arrangement can thus be produced without complex cleaning steps and in addition, the quality of the dielectric in the capacitor is extremely high.

Abstract translation: 将说明制造集成电路装置（100）包括一个电容器（112）的方法。 介电层（160）是通过两步蚀刻工艺的装置和由硬掩模的装置图案化。 硬掩模是在电绝缘硬掩模的情况下除去。 在电路装置（100）中的硬掩模的导电硬掩模部分的情况下，可以保持。 该集成电路可以毫不复杂的纯化步骤来制备。 在电容器中的电介质的质量也很高。

公开(公告)号：WO03015163A2

公开(公告)日：2003-02-20

申请号：PCT/EP0207313

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG ,  BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249

CPC classification number: H01L21/8249

Abstract: The invention relates to a method for the parallel production of an MOS transistor in an MOS area of a substrate (1) and a bipolar transistor in a bipolar area of said substrate (1). The method comprises the creation of an MOS preconditioning structure in the MOS area, whereby the MOS preconditioning structure contains a region (13) provided for a channel, a gate dielectric (14), a gate electrode layer (15, 19) and a masking layer (21a, 21b, 22) on the gate electrode layer (15, 19). In addition, a bipolar preconditioning structure is created in the bipolar area, said structure comprising a conductive layer (20) and a masking layer (21a, 21b, 22) on the conductive layer (20). To establish a gate electrode and a base connection region, the gate electrode layer (15, 19) and the conductive layer (20) are jointly structured. The invention also relates to the simultaneous creation of isolating spacer layers (30, 31) on lateral walls of the gate electrode layer in the MOS area and on the conductive layer in the bipolar area by the application of a first (30) and second spacer layer (31). The isolating spacer layers define the regions to be doped in the MOS area and isolate a base region and an emitter region in the bipolar area. Finally, the first spacer layer (30) and the second spacer layer (31) are selectively etched in the MOS and bipolar areas.

Abstract translation: 本发明提供了一种在衬底（1）的MOS区中并联制造MOS晶体管的方法以及在衬底（1）的双极区中的双极晶体管的制造方法。 该方法包括在MOS区中生成MOS准备结构，该MOS准备结构包括为沟道设置的区域（13），栅极电介质（14），栅电极层（15,19）和掩模层（21a， 21b，22）设置在栅电极层（15,19）上。 此外，在双极区中产生双极预备结构，双极区包括导电层（20）上的导电层（20）和掩模层（21a，21b，22）。 为了限定栅极电极和基极端子区域，执行栅极电极层（15,19）和导电层（20）的通用结构化。 该方法还包括通过沉积第一（30）和第二间隔层（31）在MOS区栅电极层和双极导电层的侧壁上同时形成绝缘间隔层（30,31）。 在MOS区中使用绝缘间隔层来定义要掺杂的区域，并且在用于隔离基极区和发射极区的双极区中使用绝缘间隔层。 随后，执行MOS区和双极区中的第一间隔层（30）和第二间隔层（31）的选择性蚀刻。

公开(公告)号：DE50312845D1

公开(公告)日：2010-08-12

申请号：DE50312845

申请日：2003-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  HOLZ JUERGEN

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/822 ,  H01L27/04

公开(公告)号：DE50202496D1

公开(公告)日：2005-04-21

申请号：DE50202496

申请日：2002-07-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTHOLD ADRIAN ,  BOECK JOSEF ,  KLEIN WOLFGANG ,  HOLZ JUERGEN

IPC: H01L21/8249 ,  H01L27/06

Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.

公开(公告)号：DE10022660A1

公开(公告)日：2001-11-08

申请号：DE10022660

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRASSMANN ANDREAS ,  HOLZ JUERGEN

IPC: H01L31/0232

Abstract: Optical sensor comprises a substrate (1); an intermediate metal dielectric (2) and a first antireflection layer (3) arranged on the substrate; and a passivating layer (7) arranged on the dielectric. Preferred Features: A photo diode is arranged in the substrate. The dielectric is made from silicon oxide doped with arsenic, phosphorus and/or boron. The antireflection layer is arranged between the substrate and the dielectric. A second antireflection layer (6) is arranged between the dielectric and the passivating layer.

公开(公告)号：DE112006000465T5

公开(公告)日：2008-04-17

申请号：DE112006000465

申请日：2006-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  HOLZ JUERGEN

IPC: H01L21/768 ,  H01L23/532

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

公开(公告)号：DE102004039803A1

公开(公告)日：2006-03-16

申请号：DE102004039803

申请日：2004-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  HOLZ JUERGEN

IPC: H01L21/822 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H05K1/16

Abstract: Production of conductor systems with high capacitive coupling comprises: (A) forming a first dielectric (2) on a substrate (1); (B) forming a trench structure in the dielectric with a capacitor zone (KB) connected to a conductor zone (LB) whose depth:width ratio is at least three times that of the capacitor zone; (C) applying a first conductive layer until the trench structure in the conductor zone is filled; (D) forming a capacitor dielectric layer (4A) on the first conductive layer; depositing a second conductive layer on the capacitor dielectric so that the trench structure in the capacitor zone is filled; (E) planarising the resulting structure to form a first conductor (3L) which is connected to a first capacitor electrode (3E),and a second capacitor electrode (5E) which is separated from the first by a dielectric layer; and (F) applying a second dielectric (7) with a second conductor (8L) connected to the second capacitor electrode by a contact-via (V2). An independent claim is included for conductor systems produced using the method.

公开(公告)号：DE10350752A1

公开(公告)日：2005-06-09

申请号：DE10350752

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ,  HOLZ JUERGEN ,  GSCHWANDTNER ALEXANDER

IPC: C23C14/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/511 ,  H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H01L21/822 ,  H01L21/314

Abstract: Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.

公开(公告)号：DE10145724A1

公开(公告)日：2003-04-10

申请号：DE10145724

申请日：2001-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOLZ JUERGEN

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L23/28

Abstract: Production of a semiconductor structure (12) comprises: (a) applying a protective layer (10) on a semiconductor structure or on a substrate; (b) forming cracks (38) in the protective layer; (c) applying a repairing layer to the protective layer; and (d) removing the repairing layer before applying further layers and/or before carrying out further processing. An Independent claim is also included for the semiconductor structure produced by the above process. Preferably the protective layer is thicker than the repairing layer and the repairing layer is half the thickness of the largest crack. The protective layer is made from tetraethylorthosilcate (TEOS). The repairing layer is made from silicon dioxide or TEOS.