公开(公告)号：DE102004049452A1

公开(公告)日：2006-04-20

申请号：DE102004049452

申请日：2004-10-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEINLESBERGER GERNOT ,  KREUPL FRANZ ,  DUESBERG GEORG STEFAN ,  HARTWICH JESSICA ,  DREESKORNFELD LARS

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/43

Abstract: A microelectronic semiconductor element comprises at least one electrode comprising a carbon-containing layer. Preferably the element is a FET having a gate electrode and a source/drain electrode comprising the carbon-containing layer. An independent claim is also included for a production process for the above.

公开(公告)号：AU2003293923A1

公开(公告)日：2004-07-22

申请号：AU2003293923

申请日：2003-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DREESKORNFELD LARS ,  HARTWICH JESSICA ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  SPECHT MICHAEL

IPC: G11C11/21 ,  G11C11/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

公开(公告)号：DE10233663A1

公开(公告)日：2004-02-19

申请号：DE10233663

申请日：2002-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DREESKORNFELD LARS ,  ROESNER WOLFGANG ,  HARTWICH JESSICA

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

Abstract: Production of a SOI substrate comprises preparing a SOI substrate by: (a) embedding a trenched oxide layer (BOX) between a crystalline silicon layer and a silicon substrate (Si); (b) applying a hard mask layer on at least one region of the silicon layer; (c) forming a window in the hard mask layer to expose the silicon layer in the window region; (d) removing the silicon layer in the window region by dry etching from a first silicon layer thickness to a second silicon layer thickness; and (e) removing the silicon layer in the window region by local oxidation of the silicon and wet chemical etching of the silicon oxide formed to a third silicon layer thickness.

公开(公告)号：DE10260334A1

公开(公告)日：2004-07-15

申请号：DE10260334

申请日：2002-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  DREESKORNFELD LARS ,  HARTWICH JESSICA

IPC: G11C11/21 ,  G11C11/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

公开(公告)号：DE10247007B3

公开(公告)日：2004-06-24

申请号：DE10247007

申请日：2002-10-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  KRETZ JOHANNES ,  DREESKORNFELD LARS

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78

Abstract: Semiconductor device comprises a substrate (SUB), an insulating layer (BOX) arranged on the substrate, and a first transistor (10) and a second transistor (20) each having a channel region (30-1, 30-2) extending between a source connection and a drain connection. Each channel region is formed in a bar made from a semiconductor material arranged on the upper surface of the insulating layer. The first transistor is a double gate bar transistor with a double gate electrode (34-1) arranged on opposite-lying bar side surfaces (32) and has a bar width between the bar side surfaces so that a bar section lying between the electrode can be completely depleted. An Independent claim is also included for a process for the production of the semiconductor device.

公开(公告)号：DE10260334B4

公开(公告)日：2007-07-12

申请号：DE10260334

申请日：2002-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  DREESKORNFELD LARS ,  HARTWICH JESSICA

IPC: G11C11/21 ,  G11C11/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792

公开(公告)号：DE102004044444A1

公开(公告)日：2006-03-16

申请号：DE102004044444

申请日：2004-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROETER RAINER ,  DREESKORNFELD LARS ,  ILICALI GUERKAN ,  HARTWICH JESSICA

IPC: H01L21/84 ,  H01L27/12

Abstract: In a process to manufacture a semiconductor device with a number of layers, a semiconductor layer is applied to a substrate and structured with the aid of a mask. The process also forms a trench with a mask over an exposed part of the substrate. An electrical insulation zone is formed on the trench sidewall, over which an electrically conducting material is placed.

公开(公告)号：DE102004030552A1

公开(公告)日：2006-02-02

申请号：DE102004030552

申请日：2004-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTWICH JESSICA ,  DREESKORNFELD LARS ,  SCHROETER RAINER ,  STEINLESBERGER GERNOT

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

公开(公告)号：DE102006001680B3

公开(公告)日：2007-08-09

申请号：DE102006001680

申请日：2006-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN JOHANNES R ,  SPECHT MICHAEL ,  DREESKORNFELD LARS

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：DE102005012661A1

公开(公告)日：2006-10-05

申请号：DE102005012661

申请日：2005-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTWICH JESSICA ,  DREESKORNFELD LARS ,  RISCH LOTHAR

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/84 ,  H01L29/78

Abstract: The device has a mesa structure adjacent to a substrate boundary surface (14) on an electrical insulating layer. A mesa insulation area (22) that is adjacent to the surface is adjoined to the structure over a mesa boundary surface and includes a gate contact area. An electrically conductive gate is adjoined to a channel and stands in electrically conductive connection with the gate contact area in a contact position. The mesa structure and the mesa insulation area are completely enclosed in the direction parallel to the substrate boundary surface. The channel that is adjacent to the electrical insulating layer is formed in the mesa structure. The mesa insulation area is adjoined to an auxiliary structure (24) that is adjacent to the substrate boundary surface, over an auxiliary structure boundary surface. An independent claim is also included for a method of manufacturing a semiconductor device.