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    3.
    发明专利
    未知

    公开(公告)号：DE10054172C2

    公开(公告)日：2002-12-05

    申请号：DE10054172

    申请日：2000-11-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GEHRING OLIVER

    IPC: H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8247

    Abstract: A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.

    Semiconductor switching element used as a CMOS transistor has a control layer that extends in the same way as a contact layer up to a wiring layer
    5.
    发明专利
    Semiconductor switching element used as a CMOS transistor has a control layer that extends in the same way as a contact layer up to a wiring layer 未知

    公开(公告)号：DE10050362A1

    公开(公告)日：2002-05-02

    申请号：DE10050362

    申请日：2000-10-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GEHRING OLIVER

    IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    Abstract: Semiconductor switching element comprises a substrate (1); a source region (2) and a drain region (3) for forming a channel region in the substrate; a dielectric layer (4) formed over the channel region; a control layer (5') for controlling the element; a contact layer (7) for contacting the source region and the drain region; an insulating layer (6) for insulating the contact layer and the control layer; and a wiring layer (8) for connecting the contact layer. The control layer extends in the same way as the contact layer up to the wiring layer. An Independent claim is also included for a process for the production of a semiconductor switching element. Preferred Features: The control layer and the contact layer are made from the same material, preferably a metal or doped semiconductor. The insulating layer is a BPSG, PSG or BSG layer.

    6.
    发明专利
    未知

    公开(公告)号：DE50115427D1

    公开(公告)日：2010-05-20

    申请号：DE50115427

    申请日：2001-12-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GEHRING OLIVER ,  LANGHEINRICH WOLFRAM

    IPC: H01L27/105 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/11568 ,  H01L27/11573

    Abstract: Production of embedded non-volatile semiconductor storage cells comprises forming a first insulating layer (2) on a substrate (1) in a high voltage region, a storage region and a logic region; removing the insulating layer in the storage region; forming a second insulating layer (3) in the high voltage region, storage region and logic region; forming and structuring a charge-storing layer (5) with a third insulating region (6) in the storage region; removing the insulating layers and the charge-storing layer; forming a fourth insulating layer in the high voltage region, storage region and logic region; and forming and structuring a conducting control layer (8). Preferred Features: A 20-25 nm thick oxide layer is deposited in the first step. A 7-10 nm thick tunnel oxide layer is thermally formed in the third step.

    7.
    发明专利
    未知

    公开(公告)号：DE50114315D1

    公开(公告)日：2008-10-23

    申请号：DE50114315

    申请日：2001-09-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GEHRING OLIVER

    IPC: H01L29/788 ,  H01L29/423

    Abstract: A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.

    8.
    发明专利
    未知

    公开(公告)号：DE59907769D1

    公开(公告)日：2003-12-24

    申请号：DE59907769

    申请日：1999-05-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GEHRING OLIVER ,  RUF DR ,  SCHMIDBAUER SVEN

    IPC: A61K31/535 ,  C23C14/16 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56 ,  H01L21/285 ,  H01L21/768

    Abstract: A process for producing metal-containing layers, in particular metal-containing diffusion barriers, contact layers and/or antireflection layers. The process according to the invention has a first step in which a metal layer having a predetermined thickness at an elevated temperature is applied to a semiconductor structure. Next, the metal layer is cooled in a nitrogen-containing atmosphere, resulting in a metal nitride layer being formed.

    9.
    发明专利
    未知

    公开(公告)号：DE10037447C2

    公开(公告)日：2002-06-27

    申请号：DE10037447

    申请日：2000-07-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRADL STEPHAN ,  GEHRING OLIVER ,  HEITZSCH OLAF

    IPC: H01L21/82 ,  G11C27/00 ,  H03K19/0175 ,  H03K19/173 ,  H01L23/58 ,  H01L29/788

    Abstract: The electrical characteristic of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding and/or extracting electrical charge, the analog electronic unit is put into a state which permanently determines the analog electrical characteristics of the unit. In particular, the floating gate of an EEPROM cell is charged up to a freely selectable charge value lying within a continuous range.

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